78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
PRELIMINARY DATASHEET
AUGUST 2003
DESCRIPTION
The 78P2341JAT is a low-power, single channel
DS3/E3/STS1 transceiver IC with integrated Jitter
Attenuator (JAT). It includes clock recovery and
transmitter pulse shaping functions for applications
using 75-ohm coaxial cable at distances up to 1350
feet. These applications include DSLAMs, T1,3/E1,3
digital multiplexers, SONET Add/Drop multiplexers,
PDH equipment, DS3 to Fiber optic and microwave
modems, and ATM WAN access for routers and
switches.
The receiver recovers clock and data from a B3ZS
or HDB3 coded AMI signal. It can compensate for
over 12dB of cable and 6dB of flat loss. The
transmitter generates a signal that meets the
standard pulse shape requirements. It has an
integrated B3ZS/HDB3 ENDEC with a receive line
code violation detector, a loop-back mode, a clock
polarity selection mode, and the ability to receive a
DSX3 monitor signal.
FEATURES
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Transmit and receive interface for E3, DS3 and
STS-1 applications
Designed for use with 75 ohm coaxial cable up
to 1350 ft long end-to-end or up to 900 ft long
from a DS3 cross-connect
Receive DS3-high and DSX3 monitor signals
Local and Remote loopback
Selectable B3ZS/HDB3 ENDEC with line code
violation detector
Standards-based LOS function
Optional serial-port based mode selection and
channel status monitoring
Receiver AGC corrects for up to 6dB of flat loss
Adaptive digital clock recovery (uses line-rate
reference clock input)
Receive output clock maintains nominal line-rate
frequency at all times
Fully integrated Jitter Attenuator (no external
VCXO required) configurable for transmit or
receive path
Transmit line fault monitor
Requires no external current-setting resistor or
loop filter components
Single 3.3V supply operation
Available in 28-pin PLCC or 48-pin TQFP
STANDARDS
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Jitter Tolerance: Telcordia GR-499-CORE [DS3]
and GR-253-CORE [STS1], ITU-T G.823 [E3]
and G.824 [DS3]
Loss of Signal: ITU-T G.775
Jitter Transfer: ETSI TBR-24 1997 [E3];
Telcordia GR-499-CORE [DS3] and GR-253-
CORE [DS3/STS1]
BLOCK DIAGRAM
Controls Flags
RLBK
LBO E3 DS3
TXEN
Transmit
Monitor
TXNW
TPOS
TNEG
TCLK
Jitter
Attenuator
RPOS
RNEG
RCLK
B3ZS /
HDB3
Encoder
Pulse
Shaper
LOUTP
LOUTN
Attenuator
ENDEC
B3ZS /
HDB3
Decoder
Data
Detector
Adaptive
Equalizer
AGC
LINP
LINN
TCLKP
RCLKP
Power
Distribution
Clock
Recovery
Signal
Detector
LLBK
MON
LOS
CKREF
PDTX PDRX
SCK
SDIO
Control
Registers
Master
Bias
Generator
CKREF
-1-
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
