DS_6618_005
78M6618 Data Sheet
2.5.5 SPI Slave Port (MISSION Mode)
Table 24: SPI Slave Port (MISSION Mode) Timing
Parameter
Condition
Min
1
Typ
Max
Unit
µs
tSPIcycPCLK cycle time
tSPILeadEnable lead time
tSPILagEnable lag time
15
0
ns
ns
tSPIWPCLK pulse width:
High
Low
40
40
ns
ns
tSPISCKPCSZ to first PCLK fall
Ignore if PCLK is low
when PCSZ falls.
2
ns
tSPIDISDisable time
0
ns
ns
ns
ns
tSPIEVPCLK to Data Out
tSPISUData input setup time
tSPIHData input hold time
15
10
5
PCSZ
tSPILead
PCLK
tSPIcyc
tSPILag
tSPIW
tSPIEV
tSPIW
tSPIDIS
tSPISCK
PSDO
PSDI
MSB OUT
MSB IN
LSB OUT
tSPIH
LSB IN
Figure 5: SPI Slave Port (MISSION Mode) Timing
Rev. 1.4
23
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
