78M6612 Data Sheet
DS_6612_001
Specifically, when SECURE is set:
•
•
The ICE is limited to bulk Flash erase only.
Page zero of Flash memory, the preferred location for the user’s preboot code, may not be
page-erased by either MPU or ICE. Page zero may only be erased with global Flash erase.
•
Writes to page zero, whether by MPU or ICE are inhibited.
The SECURE bit is to be used with caution! Inadvertently setting this bit will inhibit access to
the part via the ICE interface, if no mechanism for actively resetting the part between reset and
erase operations is provided.
1.5.13 Test Ports
TMUXOUT Pin: One out of 16 digital or 8 analog signals can be selected to be output on the TMUXOUT
pin. The function of the multiplexer is controlled with the I/O RAM register TMUX (0x20AA[4:0]), as
shown in Table 43.
Table 43: TMUX[4:0] Selections
TMUX[4:0]
Mode
Analog
Analog
Analog
Analog
Analog
Analog
–
Function
0
1
DGND
Reserved
2
DGND
3-5
Reserved
6
VBIAS
7
Not used
8-0x0F
0x10 – 0x13
0x14
0x15
0x16 – 0x17
0x18
0x19
0x1A
0x1B
0x1C
0X1D
Reserved
–
Not used
Digital
Digital
RTM (Real time output from CE)
WDTR_EN (Comparator 1 Output AND V1LT3)
Not used
Digital
Digital
Digital
Digital
–
RXD (from Optical interface, w/ optional inversion)
MUX_SYNC
CK_10M (10 MHz clock)
CK_MPU (MPU clock)
Reserved
Digital
RTCLK (output of the oscillator circuit, nominally
32,786 Hz)
0X1E
0X1F
Digital
Digital
CE_BUSY (busy interrupt generated by CE, 396 µs)
XFER_BUSY (transfer busy interrupt generated by
CE, nominally every 999.7 ms)
50
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
