78M6612 Data Sheet
DS_6612_001
2.2 System Timing Summary
Figure 16 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and
the two serial output streams. In this example, MUX_DIV[1:0] = 4 and FIR_LEN = 1 (384). The duration of
each MUX frame is 1 + MUX_DIV[1:0] * 2 if FIR_LEN = 0 (288), and 1 + MUX_DIV[1:0] * 3 if FIR_LEN = 1
(384). An ADC conversion will always consume an integer number of CK32 clocks. Followed by the
conversions is a single CK32 cycle where the bandgap voltage is allowed to recover from the change in
CROSS.
Each CE program pass begins when ADC0 (channel IA) conversion begins. Depending on the length of
the CE program, it may continue running until the end of the ADC3 (VB) conversion. CE opcodes are
constructed to ensure that all CE code passes consume exactly the same number of cycles. The result
of each ADC conversion is inserted into the CE DRAM when the conversion is complete. The CE code is
written to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded
into DRAM is shown in Figure 16.
Figure 16 also shows that the serial RTM data stream begins transmitting at the beginning of state ‘S.’
RTM, consisting of 140 CK cycles, will always finish before the next code pass starts.
ADC MUX Frame
MUX_DIV
MUX_DIV[1:0]
= 01 (4 conversions) is shown
Conversions,
Settle
ADC
CK32
150
0
MUX_SYNC
MUX STATE
S
1
2
3
S
ADC EXECUTION
ADC0
450
ADC1
900
ADC2
1350
ADC3
180
CE
0
CE_EXECUTION
0
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5)
MAX CK COUNT
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
RTM TIMING
140
RTM
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers
CK32
MUX_SYNC
CKTEST
0
1
30 31
0
1
30
31
0
1
30
31
0
1
30
31
TMUXOUT/RTM
FLAG
FLAG
FLAG
FLAG
SB
IGN
S
SB
SB
SB
L
IGN
IGN
IGN
RTM DATA0 (32 bits)
RTM DATA1 (32 bits)
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
L
L
L
S
S
S
Figure 17: RTM Output Format
52
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
