DS_6612_001
78M6612 Data Sheet
Watchdog Timer Reload Register (WDTREL)
Table 23: The WDTREL Register
MSB
LSB
7
6
5
4
3
2
1
0
Bit
Symbol Function
Prescaler select bit. When set, the watchdog is clocked through an
additional divide-by-16 prescaler.
WDTREL[7]
7
WDTREL[6]
to
WDTREL[0]
Seven bit reload value for the high-byte of the watchdog timer. This
value is loaded to the WDT when a refresh is triggered by a consecutive
setting of bits WDT and SWDT.
6-0
The WDTREL register can be loaded and read at any time.
1.4.9 Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s)
located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and
IEN2.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate
in other parts of the 78M6612, for example the CE, DIO, RTC EEPROM interface.
1.4.9.1 Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 37.
Once interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt
service is terminated by a return from the RETI instruction. When a RETI is performed, the MPU will
return to the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the MPU will also indicate this by setting a flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set.
On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the
appropriate vector address, if the following conditions are met:
•
•
•
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or
IP1.
Rev. 1.2
31
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
