78M6612 Data Sheet
DS_6612_001
Special Function Registers for the WD Timer
Interrupt Enable 0 Register (IEN0)
Table 20: The IEN0 Register
MSB
EAL
LSB
EX0
WDT
ET2
ES0
ET1
EX1
ET0
Bit
Symbol Function
WDT Watchdog timer refresh flag.
IEN0[6]
Set to initiate a refresh of the watchdog timer. Must be set directly before
SWDT is set to prevent an unintentional refresh of the watchdog timer.
WDT is reset by hardware 12 clock cycles after it has been set.
Note: The remaining bits in the IEN0 register are not used for watchdog control.
Interrupt Enable 1 Register (IEN1)
Table 21: The IEN1 Register
MSB
LSB
EXEN2 SWDT
EX6
EX5
EX4
EX3
EX2
–
Bit
Symbol Function
IEN1[6]
SWDT
Watchdog timer start/refresh flag.
Set to activate/refresh the watchdog timer. When directly set after
setting WDT, a watchdog timer refresh is performed. Bit SWDT is reset by
the hardware 12 clock cycles after it has been set.
Note: The remaining bits in the IEN1 register are not used for watchdog control.
Interrupt Priority 0 Register (IP0)
Table 22: The IP0 Register
MSB
LSB
IP0.0
–
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
Bit
Symbol Function
IP0[6]
WDTS
Watchdog timer status flag. Set when the watchdog timer was started.
Can be read by software.
Note: The remaining bits in the IP0 register are not used for watchdog control.
30
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
