DS_6612_001
78M6612 Data Sheet
Timer/Counter Mode Control Register (PCON)
The SMOD bit in the PCON register doubles the baud rate when set.
Table 19: The PCON Register
MSB
LSB
–
SMOD
–
–
–
–
–
–
Bit
Symbol Function
SMOD Baud rate control.
PCON[7]
1.4.8 WD Timer (Software Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles.
After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a
16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once
the watchdog is started, it cannot be stopped unless the internal reset signal becomes active.
Note: It is recommended to use the hardware watchdog timer instead of the software
watchdog timer.
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register
enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6
in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing
the state of the WDT timer.
Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request
signal from becoming active. This requirement imposes an obligation on the programmer to issue two
instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay
allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has not
been set, the WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of
the WDTREL register and the WDT is automatically reset. Since the WDT requires exact timing, firmware
needs to be designed with special care in order to avoid unwanted WDT resets. Teridian strongly
discourages the use of the software WDT.
Rev. 1.2
29
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
