DS_8024RN_020
73S8024RN Data Sheet
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Reset and Clock for card interface, RST, CLK
VOH
VOL
Output level, high
Output level, low
0.9 VCC
0
VCC
0.3
0.1
0.3
30
V
V
IOH =-200μA
IOL=200μA
IOL = 0
V
Output voltage when outside
of session
VINACT
IOL = 1mA
V
IRST_LIM
ICLK_LIM
Output current limit, RST
Output current limit, CLK
CLK slew rate
mA
mA
V/ns
V/ns
70
CLKSR3V
CLKSR5V
Vcc = 3V
Vcc = 5V
0.3
0.5
CLK slew rate
CL = 35pF for CLK,
10% to 90%
CL = 200pF for RST,
10% to 90%
8
ns
ns
tR, tF
Output rise time, fall time
Duty cycle for CLK
100
CL =35Pf,
45
55
%
δ
FCLK ≤ 20MHz
12.5 Characteristics: Digital Signals
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Digital I/O Except for OSC I/O
VIL
Input Low Voltage
-0.3
0.8
VDD + 0.3
0.45
V
V
V
V
VIH
Input High Voltage
Output Low Voltage
Output High Voltage
Pull-up resistor, OFF
Input Leakage Current
0.7 VDD
VOL
VOH
ROUT
|IIL1|
IOL = 2mA
IOH = -1mA
VDD - 0.45
16
-5
21
24
5
kΩ
μA
GND < VIN < VDD
Oscillator (XTALIN) I/O Parameters
VILXTAL
VIHXTAL
IILXTAL
Input Low Voltage - XTALIN
Input High Voltage - XTALIN
-0.3
0.3 VDD
VDD+0.3
V
V
0.7 VDD
Input Current -
XTALIN
Max freq. Osc or external
clock
GND < VIN < VDD
-30
30
27
52
μA
MHz
%
fMAX
tR/F < 10% fIN,
45% < δCLK < 55%
External input duty cycle limit
48
δin
Rev. 1.8
19
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
