DS_8023C_019
73S8023C Data Sheet
OFF is low by
OFF is low by
card extracted
any fault
PRES
OFF
CMDVCC
VCC
outside card session
within card session
within card
session
Figure 8: Timing Diagram – Management of the Interrupt Line OFF
10 I/O Circuitry and Timing
The I/O, AUX1, and AUX2 pins are in the low state after power-on reset and they are in the high state
when the activation sequencer turns on the I/O reception state. See Section 8 Activation and
Deactivation for more details on when the I/O reception is on.
The state of the I/OUC, AUX1UC, and AUX2UC pins is high after power-on reset. Within a card session
and when the I/O reception state is on, the first I/O line on which a falling edge is detected becomes the
input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected,
both I/O lines return to their neutral state.
Figure 9 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output.
The delay between the I/O signals is shown in Figure 10.
In order to be compliant to the NDS specifications, a 27 pF capacitor must be added between pins
I/O (C7) and GND (C5) at the smart card connector.
Rev. 1.5
15
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
