73S8023C Data Sheet
DS_8023C_019
CMDVCC
OFF
-- OR --
VCC
IO
RSTIN
RST
STROBE
CLK
t0 t1 t2 t3
t
4
t5
t
t
t
0
1
2
- Deactivation starts after CMDVCC is set high or OFF falls due to card removal or fault
- RST falls approx. 0.5us after deactivation begins
- CLK falls approx. 7.5us after RST falls
t
3
- IO falls approx 2us after CLK falls
t
4
5
- VCC is shut down
t
- VCC goes to 0 after discharge of VCC capacitor, approx 100us after deactivation begins
(Note: Host should set STROBE low when CMDVCC is set high, otherwise CLK may be truncated.
CLK truncation may occur if an OFF event is triggered)
Figure 4: Synchronous Deactivation Operation – CKSEL = High
8.3 Activation Sequence (Asynchronous Mode)
The 73S8023C smart card interface IC has an internal 10 ms delay at power-on reset or upon application
of VDD > VDDF or upon exit of Power Down mode. The card interface may only be activated when OFF is
high which indicates a card is present. No activation is allowed at this time. CMDVCC (edge triggered)
must then be set low to activate the card.
The following steps list the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low while the RSTIN is low:
1. CMDVCC is set low.
2. Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation,
the voltage VCC to the card becomes valid during t1. If VCC does not become valid, then OFF goes
low to report a fault to the system controller, and the power VCC to the card is turned off.
3. Turn I/O (AUX1, AUX2) to reception mode at the end of t2.
4. CLK is applied to the card at the end of t3.
5. RST is a copy of RSTIN after t4. RSTIN may be set high before t4, however the sequencer won’t set
RST high until 42000 clock cycles after the start of CLK.
12
Rev. 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
