73S8014R Data Sheet
DS_8014R_012
3.6 Activation Sequence
The 73S8014R smart card interface ICs have an internal 10ms delay on the application of VDD where VDD >
VDDF. No activation is allowed during this 10ms period. The CMDVCC (edge triggered) signal must then be set
low to activate the card. In order to initiate activation, the card must be present; there can be no VDD fault.
The following steps show the activation sequence and the timing of the card control signals when the system
controller sets CMDVCC low while the RSTIN is low:
-
-
CMDVCC is set low at t0.
VCC will rise to the selected level and then the internal VCC control circuit checks the presence of VCC at
the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not
valid at t1, the OFF goes low to report a fault to the system controller, and VCC to the card is shut off.
Turn I/O to reception mode at t2.
CLK is applied to the card at t3.
RST is a copy of RSTIN after t3.
-
-
-
CMDVCC
VCC
I/O
CLK
RSTIN
RST
t0
t2
t3
t1
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5μs, I/O goes to reception state
t3 = >0.5μs, CLK starts, RST to become the copy of RSTIN
Figure 4: Activation Sequence – RSTIN Low When CMDVCC Goes Low
The following steps show the activation sequence and the timing of the card control signals when the system
controller pulls the CMDVCC low while the RSTIN is high:
-
-
CMDVCC is set low at t0.
VCC will rise to the selected level and then the internal VCC control circuit checks the presence of VCC at
the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not
valid at t1, the OFF goes low to report a fault to the system controller, and VCC to the card is shut off.
At the fall of RSTIN at t2, CLK is applied to the card
-
-
RST is a copy of RSTIN after t2.
18
Rev. 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
