73S8014R Data Sheet
DS_8014R_012
3.2 System Controller Interface
Three digital inputs allow direct control of the card interface by the host. The 73S8014R is controlled as follows:
Pin CMDVCC: When asserted low, starts an activation sequence
Pin RSTIN: controls the card RST signal (when enabled by the sequencer)
Pin 5V/#V: Defines the card VCC voltage (5V when high and 3V when low)
Card clock frequency can be controlled by 2 digital inputs:
CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input clock frequency (crystal
or external clock)
Note: The maximum CLK frequency is 20MHz. Therefore, if using an input clock source greater than 20MHz, a
divisor rate of 2X or higher must be used.
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card
presence only (Low = No card in the reader). When CMDVCC is asserted low (Card activation sequence
requested from the host), low level on OFF means a fault has been detected (e.g. card removal during card
session, voltage fault, or over-current fault) that automatically initiates a deactivation sequence.
3.3 Power Supply and Voltage Supervision
The 73S8014R smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by
the digital input 5V/#V of the 73S8014R. This regulator is able to provide either 3V or 5V card voltage from the
power supply applied on the VPC pin. The voltage regulator can provide a current of at least 65mA on VCC for
both 3V and 5V that complies with EMV 4.0.
Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to
interface with the system controller. A card deactivation sequence is forced upon fault of any of this voltage
supervisor. One voltage supervisor constantly monitors the VDD voltage. It is used to initialize the ISO 7816-3
sequencer at power-on, and to deactivate the card at power-off or upon fault. The voltage threshold of the VDD
voltage supervisor is internally set by default to 2.33V nominal. However, it may be desirable, in some
applications, to modify this threshold value. The pin VDDF_ADJ is used to connect an external resistor REXT to
ground to change the VDD fault voltage to another value, VDDF. The resistor value is defined as follows:
REXT = 56kΩ /(VDDF - 2.33)
An alternative (more accurate) method of adjusting the VDD fault voltage is to use a resistive network of R3 from
the pin to supply and R1 from the pin to ground (see Figure 3). In order to set the new threshold voltage, the
equivalent resistance must be determined. This resistance value will be designated Kx. Kx is defined as
R1/(R1+R3). Kx is calculated as:
Kx = (2.789 / VTH) - 0.6125 where VTH is the desired new threshold voltage.
To determine the values of R1 and R3, use the following formulas.
R3 = 24000 / Kx
R1 = R3*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7V is desired, solving for Kx gives:
Æ Kx = (2.789 / 2.7) - 0.6125 = 0.42046.
Solving for R3 gives:
Solving for R1 gives:
Æ R3 = 24000 / 0.42046 = 57080.
Æ R1 = 57080 *(0.42046 / (1 – 0.42046)) = 41412.
Using standard 1 % resistor values gives R3 = 57.6KΩ and R1 = 42.4KΩ.
These values give an equivalent resistance of Kx = 0.4228, a 0.6% error.
If the 2.33V default threshold is used, this pin must be left unconnected.
16
Rev. 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
