73S8014RT Data Sheet
DS_8014RT_015
Table 1: 73S8014RT 20-Pin SOP Pin Definitions
Pin Name
Card Interface
I/O
RST
CLK
14
15
17
IO
O
O
Card I/O: Data signal to/from card. Includes an 11K pull-up
resistor to V
CC.
Card reset: provides reset (RST) signal to card.
Card clock: provides clock signal (CLK) to card. The rate of this
clock is determined by the external crystal frequency or
frequency of the external clock signal applied on XTALIN and
CLKDIV selections.
Card Presence switch: active high indicates card is present.
Includes a high-impedance pull-down current source.
Card power supply – logically controlled by sequencer, output of
LDO regulator. Requires an external filter capacitor to the card
GND.
Card ground.
Logic low on one or both of these pins will cause the LDO
regulator to ramp the Vcc supply to the smart card and smart
card interface to the value described in the following table:
CMDVCC#
Vcc Output Voltage
CMDVCC%
0
0
1.8V
0
1
5.0V
1
0
3.0V
1
1
Vcc Off
Note: See
for more details.
Sets the divide ratio from the XTAL oscillator (or external clock
input) to the card clock. These pins include a pull-up resistor for
CLKDIV1 and CLKLDIV2 to provide a default rate of divide by
two.
CLKDIV1
CLKDIV2
CLOCK RATE
0
0
XTALIN/6
0
1
XTALIN/4
1
1
XTALIN/2
1
0
XTALIN
Interrupt signal to the processor. Active Low – Multi-function
indicating fault conditions and card presence. Open drain output
configuration. It includes an internal 20kΩ pull-up to V
DD.
Reset Input: This signal is the reset command to the card.
System controller data I/O to/from the card. Includes an 11K
pull-up resistor to V
DD.
Pin
Number Type
Equivalent
Circuit
Description
PRES
VCC
GND
19
18
16
I
PSO
GND
–
Host Processor Interface
CMDVCC%
6
I
CMDVCC#
7
I
CLKDIV1
CLKDIV2
20
5
I
OFF
RSTIN
I/OUC
1
2
3
O
I
IO
6
Rev. 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
