73S8014RT Data Sheet
DS_8014RT_015
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Interface Requirements – Data Signals: I/O and Host Interfaces: I/OUC.
ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC.
IOH =0
0.9 VDD
0.75 VDD
0.9 VCC
VDD+0.1
VDD+0.1
VCC+0.1
V
V
V
Output level, high (I/OUC)
IOH = -40μA
IOH =0
VOH
IOH = -40μA (VCC
=
Output level, high (I/O)
0.75 VCC
VCC+0.1
V
3/5V), IOH = -20μA
(VCC = 1.8V)
Output level, low (I/OUC)
Output level, low (I/O)
IOL=1mA
Vcc = 5V
Vcc = 3V
Vcc = 1.8V
0.3
0.45
V
V
VOL
0.2
V
0.15 VCC
VDD + 0.3
VCC+0.30
0.8
V
Input level, high
Input level, high (I/O)
Input level, low
1.8
0.6 VCC
-0.3
V
VIH
V
V
VIL
Vcc = 5V, 3V
Vcc = 1.8V
IOL = 0
-0.3
0.8
V
Input level, low (I/O)
-0.3
0.2 VCC
0.1
V
V
Output voltage when outside
of session
VINACT
IOL = 1mA
VIH = VCC
VIL = 0
0.3
V
ILEAK
IIL
Input leakage
10
μA
mA
Input current, low
0.65
For output low,
shorted to VCC
through 33 Ω
ISHORTL
ISHORTH
tR, tF
Short circuit output current
Short circuit output current
Output rise time, fall times
15
15
mA
mA
ns
For output high,
shorted to ground
through 33 Ω
CL = 80pF, 10% to
90%.
100
tIR, tIF
RPU
Input rise, fall times
Internal pull-up resistor
Maximum data rate
1
14
1
μs
kΩ
Output stable for
>400ns
8
11
MHz
ns
FDMAX
TFDIO
Delay, I/O to I/OUC, I/OUC to
I/O, (respectively falling edge
to falling edge and rising
edge to rising edge)
Edge from master to
slave, measured at
50%
60
100
15
200
TRDIO
CIN
ns
Input capacitance
10
pF
10
Rev. 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
