DS_8014RT_015
73S8014RT Data Sheet
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Reset and Clock for Card Interface, RST, CLK
VOH
Output level, high
0.9 VCC
VCC
0.45
0.2
V
V
IOH =-200μA
0
0
0
IOL=200μA, VCC = 5V
IOL=200μA, VCC = 3V
IOL=200μA, VCC = 1.8V
VOL
Output level, low
V
0.15 VCC
0.1
V
IOL = 0
V
Output voltage when
outside of session
VINACT
IOL = 1mA
0.3
V
IRST_LIM
ICLK_LIM
Output current limit, RST
Output current limit, CLK
CLK slew rate
30
mA
mA
V/ns
V/ns
70
CLKSR3V
CLKSR5V
<
0.3
0.5
CLK slew rate
Vcc = 5V
CL = 35pF for CLK,
10% to 90%
8
ns
ns
tR, tF
Output rise time, fall time
Duty cycle for CLK
CL = 200pF for RST,
10% to 90%
100
CL =35pF,
FCLK ≤ 20MHz
CL =35pF,
45
55
%
δ
FCLK < 10MHz
Vcc = 1.8V
2.5 Characteristics: Digital Signals
Table 6 lists the 73S8014RT digital signals characteristics.
Table 6: Digital Signals Characteristics
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Digital I/O Except for XTALIN and XTALOUT
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.3
1.8
0.8
VDD + 0.3
0.45
V
V
V
VIH
VOL
IOL = 2mA
VOH
ROUT
|IIL1|
Output High Voltage
Pull-up resistor, OFF
Input Leakage Current
IOH = -1mA
VDD - 0.45
V
16
-5
20
24
5
kΩ
μA
GND < VIN < VDD
GND < VIN < VDD
CLKDIV2 only
|IIL2|
Input Leakage Current
-15
15
μA
Rev. 1.0
11
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
