73S8010R
Low Cost Smart Card Interface
DATA SHEET
WARM RESET
The 73S8010R automatically asserts a warm reset to the card when instructed through the bit 1 of the I2C Control
register (bit Warm Reset). The warm reset length is automatically defined as 42,000 card clock cycles. The bit
Warm Reset is automatically reset when the card starts answering or when the card is declared mute.
IO
Warm Reset
(bit 1)
RST
t1
t2
t3
t1 > 1.5µs, Warm Reset Starts
t2 = 42000 card clock cycles, End of Warm Reset
t3 = Resets Warm Reset bit 1 when detected ATR or Mute
Figure 8 – Warm Reset operation
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© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
