73S8010C Data Sheet
DS_8010C_024
1.4
Microcontroller Interface
PIN
(SO)
23
8
PIN
Description
(QFN)
22
5
Interrupt output (negative assertion): Interrupt output signal to the
processor. A 20 kΩ pull up to V
DD
is provided internally.
Power Down control input: Active High. When Power Down (PD) mode is
activated, all internal analog functions are disabled to place the 73S8010C
in its lowest power consumption mode. Must be tied to ground when the
power down function is not used.
Serial device address bits: Digital inputs for address selection that allow
the connection of up to 8 devices in parallel. Address selections as follows:
SAD2
0
0
0
0
1
1
1
1
SAD1
0
0
1
1
0
0
1
1
SAD0
0
1
0
1
0
1
0
1
I
2
C Address (7 bits)
0x40
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
Name
INT
PWRDN
SAD0
SAD1
SAD2
1
2
3
29
30
31
Pins SAD0 and SAD1 are internally pulled-down and SAD2 is
internally pulled-up.
The default address when left unconnected is 48h.
SCL
SDA
I/OUC
AUX1UC
AUX2UC
19
20
26
27
28
18
19
26
27
28
I
2
C clock signal input.
I
2
C bi-directional serial data signal.
System controller data I/O to/from the card. Includes internal pull-up
resistor to V
DD.
System controller auxiliary data I/O to/from the card. Includes internal pull-
up resistor to V
DD.
System controller auxiliary data I/O to/from the card. Includes internal pull-
up resistor to V
DD.
6
Rev. 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
