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73S8009R-IM/F 参数 Datasheet PDF下载

73S8009R-IM/F图片预览
型号: 73S8009R-IM/F
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本通用智能卡接口 [Low Cost Versatile Smart Card Interface]
分类和应用: 模拟IC信号电路PC
文件页数/大小: 23 页 / 337 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73S8009R Data Sheet
describes the pin functions for the device.
Table 1: 73S8009R Pin Definitions
Pin
Name
I/O
AUX1
AUX2
RST
CLK
Pin
(SO28)
25
24
23
21
19
Pin
(QFN20)
15
NA
NA
13
11
Type
Description
DS_8009R_056
Card Interface
IO
IO
IO
O
O
Card I/O: Data signal to/from card. Includes a pull-up
resistor to V
CC.
AUX1: Auxiliary data signal to/from card. Includes a pull-up
resistor to V
CC.
AUX2: Auxiliary data signal to/from card. Includes a pull-up
resistor to V
CC.
Card reset: provides reset signal to card.
Card clock: provides clock signal to card. The rate of this
clock is determined by the external clock frequency
provided on pin CLKIN.
Card Presence switch: active high indicates card is present.
Should be tied to GND when not used, but includes a high-
impedance pull-down current source.
Card Presence switch: active low indicates card is present.
Should be tied to VDD when not used, but includes a high-
impedance pull-up current source.
Card power supply – logically controlled by the sequencer,
output of LDO regulator. Requires an external filter
capacitor to GND.
Card ground.
Clock source for the card clock.
This pin must be tied to GND in typical applications.
This pin must be tied to GND in typical applications.
Non-connected pin.
System interface supply voltage and supply voltage for
internal circuitry.
LDO regulator power supply source.
GND
I
Ground.
When CS = 1, the control and signal pins are configured
normally. When CS is set low,
CMDVCC%,
RSTIN, and
CMDVCC#
are latched, IOUC, AUX1UC, and AUX2UC are
set to high-impedance pull-up mode and do not pass data
to or from the smart card. Signals RDY and
OFF
are
disabled to prevent a low output and the internal pull-up
resistors are disconnected.
Interrupt signal to the processor. Active low, multi-function
indicating fault conditions and card presence. Open drain
output configuration. It includes an internal 20
kΩ pull-up
to
VDD. The pull-up is disabled in PWRDN and CS=0 modes.
Rev. 1.3
PRES
26
16
I
PRES
16
10
I
VCC
22
14
PSO
GND
CLKIN
TEST1
TEST2
NC
VDD
VPC
GND
CS
20
11
2
14
3,17,18
28
15
27
1
NA
5
19
8
NA
17
9
12
18
GND
I
Miscellaneous Inputs and Outputs
Power Supply and Ground
Microcontroller Interface
OFF
4
20
O
6