DS_8009R_056
Pin
Name
I/OUC
AUX1UC
AUX2UC
CMDVCC%
CMDVCC#
Pin
(SO28)
5
6
7
8
9
Pin
(QFN20)
1
NA
NA
2
3
73S8009R Data Sheet
Type
I/O
I/O
I/O
I
I
Description
System controller data I/O to/from the card. Includes a pull-
up resistor to V
DD.
System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to V
DD.
System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to V
DD.
Logic low on one or both of these pins will cause the LDO to
ramp the Vcc supply to the smart card and smart card
interface to the value described in the following table:
CMDVCC% CMDVCC#
V
CC
Output Voltage
0
0
1.8 V
0
1
5.0 V
1
0
3.0 V
1
1
LDO off
Refer to for additional information on the
CMDVCC%
and
CMDVCC#
operation.
RSTIN
RDY
10
12
4
6
I
O
Reset Input. This signal is the reset command to the card.
Signal to controller indicating the 73S8009R is ready
because V
CC
is above the required value after
CMDVCC%
and/or
CMDVCC#
is asserted low. A 20 KΩ pull-up resistor
to V
DD
is provided internally. The pull-up is disabled in
PWRDN and CS=0 modes.
PWRDN=1 puts the circuit into low-power mode with all
analog functions disabled. The circuit will recover from the
PWRDN state in the same manner as recovery from a POR
event, taking approximately 1 ms. PWRDN assertion when
either
CMDVCC%
or
CMDVCC#
is low has no effect and is
ignored. There is no pull-up or pull-down provided on this pin.
PWRDN
13
7
I
Rev. 1.3
7
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
