DS_8009C_025
Table 1: 73S8009C Pin Definitions
Pin
Name
Pin
Pin
Type
(QFN32) (QFN20)
Equivalent
Circuit
73S8009C Data Sheet
Description
Card Interface
I/O
AUX1
AUX2
RST
22
21
20
18
14
N/A
N/A
12
IO
IO
IO
O
Card I/O: Data signal to/from card. Includes a
pull-up resistor to V
CC.
AUX1: Auxiliary data signal to/from card.
Includes a pull-up resistor to V
CC.
AUX2: Auxiliary data signal to/from card.
Includes a pull-up resistor to V
CC.
Card reset: provides reset (RST) signal to card.
RST is the pass through signal on RSTIN.
Internal control logic will hold RST low when
card is not activated or VCC is too low.
Card clock: provides clock signal (CLK) to card.
CLK is the pass through of the signal on pin
CLKIN. Internal control logic will hold CLK low
when card is not activated or VCC is too low.
Card Presence switch: active high indicates
card is present. Should be tied to GND when
not used, but it Includes a high-impedance
pull-down current source.
Card Presence switch: active low indicates
card is present. Should be tied to V
DD
when
not used, but it Includes a high-impedance
pull-up current source.
Card power supply – logically controlled by
sequencer, output of LDO regulator.
Requires an external 0.47
µF
low ESR filter
capacitor to GND.
Card ground.
Clock signal source for the card clock.
Factory test pin. This pin must be tied to
GND in typical applications
Factory test pin. This pin must be tied to
GND in typical applications
CLK
16
10
O
PRES
14
8
I
PRES
13
N/A
I
VCC
19
13
PSO
GND
CLKIN
TEST1
TEST2
17
7
10
30
11
6
7
20
GND
I
–
–
–
–
–
Miscellaneous Inputs and Outputs
Power Supply and Ground
VDD
29
19
PSO
System interface supply voltage and supply
voltage for companion controller circuitry.
Requires a minimum of two 0.1
µF
capacitors
to ground for proper decoupling.
Rev. 1.4
7
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
