73S1217F Data Sheet
DS_1217F_002
1.7.17 Smart Card Interface Function
The 73S1217F integrates one ISO-7816 (T=0, T=1) UART, one complete ICC electrical interface as well
as an external smart card interface to allow multiple smart cards to be connected using the Teridian
73S8010x family of interface devices. Figure 16 shows the simplified block diagram of the card circuitry
(UART + interfaces), with detail of dedicated XRAM registers.
ICC Event
SCInt
Card Interrupt
ICC Pwr_event
Management
SCIE
Card
Insertion
PRES
SParCtl
Serial
UART
VccCtl/
VccTMR
TX
RX
SByteCtl
FDReg
SCCtl
Activation /
Deactivation
Sequencer
UART
T=0 T=1
VCC Card
Generation
Direct
Mode
VCC
I/O
SCECtl
SCPrtcol
Buffer / Level
Shifter
I/O ICC#1
Card and
Mode
Selection
2-Byte
Tx FIFO
STXCtl
STXData
SRXCtl
Buffer / Level
Shifter
RST
CLK
2-Byte
Rx FIFO
SCSel
SRXData
Buffer / Level
Shifter
SCCLK/SCSCLK
BGT/EGT
BGT0/1/2/3/
CWT0/1
Buffer / Level
Shifter
Timers
C4
ATRMsB/LsB
STSTO
Buffer / Level
Shifter
RLength
C8
SCDir
SCCLK
CLK ICC
Internal ICC Interface
Card Clock
Management
7.2MHz
CLKExt. ICC
SIO
SCLK
SCSCLK
XRAM Registers
SCCLK/
SCSCLK
External ICC Interface
Figure 16: Smart Card Interface Block Diagram
Card interrupts are managed through two dedicated registers SCIE (Interrupt Enable to define which
interrupt is enabled) and SCInt (Interrupt status). They allow the firmware to determine the source of an
interrupt, that can be a card insertion / removal, card power fault, or a transmission (TX) or reception (RX)
event / fault. It should be noted that even when card clock is disabled, an ICC interrupt can be generated
on a card insertion / removal to allow power saving modes. Card insertion / removal is generated from
the respective card switch detection inputs (whose polarity is programmable).
78
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
