DS_1217F_002
73S1217F Data Sheet
1.7.16 USB Interface
The 73S1217F provides a single interface, full speed -12Mbps - USB device port as per the Universal
Serial Bus Specification, Revision 2.0 (backward compatible with USB 1.1). USB circuitry gathers the
transceiver, the Serial Interface Engine (SIE), and the data buffers. An internal pull-up to VDD on D+
indicates that the device is a full speed device attached to the USB bus (allows full speed recognition by
the host without adding any external components). When using the USB interface, VDD must be between
3.0V – 3.6V in order to meet the USB VOH requirement. The interface is highly configurable under
firmware control. Control (Endpoint 0), Interrupt IN, Bulk IN and Bulk OUT transfers are supported. Four
endpoints are supported and are configured by firmware:
•
Endpoint 0, the default (Control) endpoint as required by the USB specification, is used to exchange
control and status information between the 73S1217F and the USB host.
•
•
•
•
•
•
•
Bulk IN Endpoint #1
Bulk OUT Endpoint #1
Interrupt IN Endpoint #2
The USB block contains several FIFOs used for communication.
There is a 128-byte RAM FIFO for each BULK endpoint. Maximum Bulk packet size is 64 bytes.
There is a 32-byte RAM FIFO for the interrupt endpoint. Maximum Interrupt packet size is 16 bytes.
There is a 16-byte RAM FIFO for the control endpoint. Maximum Control packet size is 16 bytes.
Figure 15 shows the simplified block diagram of the USB interface.
USB Registers
MISCtl1
VDD
0
USBCon
16-Byte FIFO
Control Endpoint 0
USB
Full Speed
12Mbps
Serial
Interface
Engine
128-Byte FIFO
D+
Bulk IN Endpoint 1
128-Byte FIFO
Bulk OUT Endpoint 1
Transceivers
D-
32-Byte FIFO
USBPEN
Interrupt IN Endpoint 2
1
48MHz
Clock
MISCtl1
Figure 15: USB Block Diagram
The USB interface consists of a Serial Interface Engine (SIE) that handles NRZI encoding/decoding, bit
stuffing / unstuffing, and CRC generation/checking. It also generates headers for packets to be
transmitted and decodes the headers of received packets. An analog transceiver interfaces with the
external USB bus. The USB interface hardware performs error checking and removes the USB protocol
fields from the incoming messages before passing the data to the firmware. The hardware also adds the
USB protocol fields to the outgoing messages coming from the firmware. The hardware implements
NRZI encoding/decoding, CRC checking/generation (both on data and token packets), device address
Rev. 1.2
75
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
