73S1217F Data Sheet
DS_1217F_002
Interrupt Enable 0 Register (IEN0): 0xA8 Å 0x00
Table 43: The IEN0 Register
MSB
EAL
LSB
EX0
WDT
ET2
ES0
ET1
EX1
ET0
Bit
Symbol
Function
IEN0.7
IEN0.6
EAL
EAL = 0 – disable all interrupts.
Watchdog timer refresh flag.
WDT
Set to initiate a refresh of the watchdog timer. Must be set directly before
SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT
is reset by hardware 12 clock cycles after it has been set.
IEN0.5
IEN0.4
IEN0.3
IEN0.2
IEN0.1
IEN0.0
–
ES0
ET1
EX1
ET0
EX0
ES0 = 0 – disable serial channel 0 interrupt.
ET1 = 0 – disable timer 1 overflow interrupt.
EX1 = 0 – disable external interrupt 1.
ET0 = 0 – disable timer 0 overflow interrupt.
EX0 = 0 – disable external interrupt 0.
Interrupt Enable 1 Register (IEN1): 0xB8 Å 0x00
Table 44: The IEN1 Register
MSB
LSB
–
SWDT
EX6
EX5
EX4
EX3
EX2
Bit
Symbol
Function
IEN1.7
IEN1.6
–
SWDT Watchdog timer start/refresh flag. Set to activate/refresh the watchdog
timer. When directly set after setting WDT, a watchdog timer refresh is
performed. Bit SWDT is reset by the hardware 12 clock cycles after it has
been set.
IEN1.5
IEN1.4
IEN1.3
IEN1.2
IEN1.1
IEN1.0
EX6
EX5
EX4
EX3
EX2
–
EX6 = 0 – disable external interrupt 6.
EX5 = 0 – disable external interrupt 5.
EX4 = 0 – disable external interrupt 4.
EX3 = 0 – disable external interrupt 3.
EX2 = 0 – disable external interrupt 2.
50
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
