73S1217F Data Sheet
DS_1217F_002
1.7.10 Real-Time Clock with Hardware Watchdog (RTC)
Figure 10 shows the block diagram of the Real Time Clock. The RTC block uses the 32768Hz oscillator
signal and divider logic to produce 0.5-second time marks. The time marks are used to create interrupts
at intervals from 0.5 seconds to 8 seconds as selected by RTC Interval (RTCINV(2:0)). The 32768Hz
oscillator can be disabled but is intended to operate at all times and in all power consumption modes.
If a 32kHz crystal is not provided, the 32 kHz oscillator should be disabled and the RTC will operate from
MCLK (96MHz) divided by 2930 (refer to the oscillator and clock generation section). The clock
generated by the high speed oscillator will not yield exactly 32768 Hz, but a frequency of approximately
32764.505119 Hz. This yields a negative 106.6 PPM (1 / 9375) error with respect to 32768Hz. The RTC
circuit provides hardware to compensate for this error by providing an offset circuit that will adjust the
RTC counter.
WDT_TIMEOUT
1/2
1
2
4
8
1/2 Second
1 Second
SELECT
INTERRUPT
RATE
RTC INT
1/2s TIMEOUT
2 Second
4 Second
8 Second
RTCCLK
START
WATCH
DOG
TIMER
RESET
DIVIDER
1/2
1
2
RTC ISR
SELECT
COUNT
RATE
1.024KHz
CLOCK
SIGN
R/W BUS
23 BIT TRIM VALUE
ADDER
R/W BUS
24 BIT ACCUMULATOR
OVERFLOW
ADVANCE
R/W BUS
IF K overflow* sign=0, extra count
32 BIT COUNTER
IF K overflow* sign=1, skip one count
Figure 10: Real Time Clock Block Diagram
54
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
