73S1217F Data Sheet
5.0V (VBUS = 0V)
DS_1217F_002
CPU clock @ 12MHz
CPU clock @ 6MHz
mA
mA
mA
18
14
22
18
27
21
CPU clock @
3.69MHz
13
19
14
11
16
23
17
14
19
28
21
17
Supply Current @ VVBAT
6.5V (VBUS = 0V)
=
CPU clock @ 24MHz
CPU clock @ 12MHz
CPU clock @ 6MHz
mA
mA
mA
mA
CPU clock @
3.69MHz
10
13
15
VDD
VDD Supply Voltage
2.7V < VPC < 6.5V,
IVDD < 40mA.
3.0
3.3
3.6
V
CPU clock @ 24MHz
CPU clock @ 12MHz
CPU clock @ 6MHz
mA
mA
mA
29
21
33.5
24
15.5
18
Supply Current
(pins 28 and 40)
CPU clock @
3.69MHz
IDD_IN
13.5
15.5
mA
Power down
8
6
50
13
μA
μA
(-40° to 85°C)
Power down (25°C)
Supply Current – pin 68
(available to external
circuitry)
IDD_OUT
Circuit ON
20
mA
mA
VCC off, IDDINTERNAL <
IVBUS
Supply Current from VBUS
0.2
0.4
1
20μA
IVBAT
IVPC
Supply Current from VBAT or
VPC
Circuit OFF
0.01
3.5
μA
VBUSON VBUS detection threshold
V
VBUSIDI
VBUS discharge current
50
μA
S
External Capacitor Values
CVPC
External filter capacitor for
VPC
μF
8.0
10.0
4.7
12.0
CVP
External filter capacitor for VP
μF
μF
2.0
0.2
10.0
1.0
CVDD
*
External filter capacitors for
VDD
CVCC should be
ceramic with low
ESR (<100MΩ).
External filter capacitor for
VCC
CVCC
0.2
0.47
1.0
μF
*Note: Recommend on 0.1μF for each VDD pin.
124
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
