73S1217F Data Sheet
DS_1217F_002
Symbol
Parameter
Condition
Min
Typ.
Max
Unit
Interface Requirements – Data Signals: I/O, AUX1 and AUX2
0.9 *
VCC
IOH =0
VCC+0.1
V
VOH
Output level, high
0.75 VCC
VCC+0.1
V
V
IOH = -40μA
VOL
VIH
VIL
Output level, low
Input level, high
Input level, low
IOL = 1mA
0.15 *VCC
0.6 *
VCC
VCC+0.30
V
-0.15
0.2 * VCC
0.1
V
V
IOL = 0
IOL = 1mA
VIH = VCC
VIL = 0
Output voltage when outside
of session
VINACT
0.3
V
ILEAK
IIL
Input leakage
10
μA
mA
mA
Input current, low
Input current, low
0.65
0.7
IIL
VIL = 0
For output low, shorted
to VCC through 33Ω
ISHORTL
ISHORTH
Short circuit output current
Short circuit output current
15
15
mA
mA
For output high, shorted
to ground through 33Ω
For I/O, AUX1, AUX2,
CL = 80pF, 10% to 90%.
For I/OUC, AUX1UC,
AUX2UC, CL = 50Pf,
10% to 90%.
tR, tF
Output rise time, fall times
100
ns
tIR, tIF
RPU
Input rise, fall times
Internal pull-up resistor
Maximum data rate
1
14
1
μs
kΩ
Output stable for >200ns
8
11
FDMAX
MHz
Reset and Clock for Card Interface, RST, CLK
VOH
VOL
Output level, high
Output level, low
0.9 * VCC
0
VCC
0.15 *VCC
0.1
V
V
IOH = -200μA
IOL = 200μA
IOL = 0
V
Output voltage when outside
of session
VINACT
IOL = 1mA
0.3
V
IRST_LIM
ICLK_LIM
Output current limit, RST
Output current limit, CLK
30
mA
mA
70
CL = 35pF for CLK,
10% to 90%
8
ns
ns
tR, tF
Output rise time, fall time
Duty cycle for CLK
CL = 200pF for RST,
10% to 90%
100
CL = 35pF, FCLK
45
55
%
δ
≤ 20MHz, CLKIN duty
cycle is 48% to 52%.
122
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
