73S1217F Data Sheet
DS_1217F_002
External Smart Card Control Register (SCECtl): 0xFE0B Å 0x00
This register is used to directly set and sample signals of External Smart Card interface. There are three
modes of asynchronous operation, an “automatic sequence” mode, and bypass mode. Clock stop per
the ISO 7816-3 interface is also supported but firmware must handle the protocol for SIO and SCLK for
I2C clock stop and start. Control for Reset (to make RST signal), activation control, voltage select, etc.
should be handled via the I2C interface when using external 73S73S8010x devices. USR(n) pins shall be
used for C4, C8 functions if necessary.
Table 90: The SCECtl Register
MSB
LSB
–
–
SIO
SIOD
–
–
SCLKLVL SCLKOFF
Bit
Symbol
Function
SCECtl.7
SCECtl.6
–
–
External Smart Card I/O. Bit when read indicates state of pin SIO for
SIOD = 1 (Caution, this signal is not synchronized to the MPU clock), when
written, sets the state of pin SIO for SIOD = 0. Ignored if not in bypass or
sync modes. In sync mode, this bit will contain the value of IO pin on the
latest rising edge of SCLK.
SCECtl.5
SIO
1 = input, 0 = output. External Smart Card I/O Direction control. Ignored if
not in bypass or sync modes.
SCECtl.4
SIOD
SCECtl.3
SCECtl.2
–
–
Sets the state of SCLK when disabled by SCLKOFF bit. If in bypass mode,
this bit directly controls the state of SCLK.
SCECtl.1
SCECtl.0
SCLKLVL
SCLKOFF
0 = SCLK enabled, 1 = SCLK disabled. When disabled, SCLK level is
determined by SCLKLVL. This bit has no effect if in bypass mode.
100
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
