DS_1217F_002
73S1217F Data Sheet
SRX Control/Status Register (SRXCtl): 0xFE08 Å 0x00
This register is used to monitor reception of data from the smart card.
Table 87: The SRXCtl Register
MSB
LSB
BIT9DAT
–
LASTRX CRCERR RXFULL RXEMTY RXOVR PARITYE
R
Bit
Symbol
Function
Bit 9 Data – When in sync mode and with MODE9/8B set, this bit will contain
SRXCtl.7
SRXCtl.6
BIT9DAT the data on IO (or SIO) pin that was sampled on the ninth CLK (or SCLK)
rising edge. This is used to read data in synchronous 9-bit formats.
–
Last RX Byte – User sets this bit during the reception of the last byte. When
byte is received and this bit is set, logic checks CRC to match 0x1D0F (T=1
mode) or LRC to match 00h (T=1 mode), otherwise a CRC or LRC error is
SRXCtl.5
LASTRX
asserted.
SRXCtl.4
SRXCtl.3
CRCERR (Read only) 1 = CRC (or LRC) error has been detected.
RXFULL
(Read only) RX FIFO is full. Status bit to indicate RX FIFO is full.
(Read only) RX FIFO is empty. This is only a status bit and does not
generate an RX interrupt.
SRXCtl.2
RXEMTY
RX Overrun – (Read Only) Asserted when a receive-over-run condition has
occurred. An over-run is defined as a byte was received from the smart
card when the RX FIFO was full. Invalid data may be in the receive FIFO.
Firmware should take appropriate action. Cleared when read. Additional
writes to the RX FIFO are discarded when a RXOVRR occurs until the
overrun condition is cleared. Will generate an RXERR interrupt.
SRXCtl.1
RXOVRR
Parity Error – (Read only) 1 = The logic detected a parity error on incoming
SRXCtl.0
PARITYE data from the smart card. Cleared when read. Will generate RXERR
interrupt.
Rev. 1.2
97
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
