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73S1215F-68IMR/F 参数 Datasheet PDF下载

73S1215F-68IMR/F图片预览
型号: 73S1215F-68IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 80515系统级芯片, USB , ISO 7816 / EMV ,密码键盘和更多 [80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More]
分类和应用: 多功能外围设备微控制器和处理器外围集成电路时钟
文件页数/大小: 136 页 / 1028 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73S1215F Data Sheet  
DS_1215F_003  
T = 0 Mode  
> EGT  
CHAR 1  
CHAR 2  
< WWT  
WWT is set by the value in the BWT registers.  
T = 1 Mode  
TRANSMISSION  
RECEPTION  
BLOCK2  
(By seting Last_TXByte and  
TX/RXB=0 during CHAR N,  
RX mode will start after last  
TX byte)  
BGT(4:0)  
BLOCK1  
CHAR  
N+1  
CHAR  
N+2  
CHAR  
N+3  
CHAR 1  
CHAR 2  
CHAR N  
TX  
> BWT  
< CWT  
EGT  
ATR Timing Parameters  
CHAR 1  
CHAR 2  
CHAR N  
IO  
TSTO(7:0)  
ATRTO(15:0)  
RST  
IWT(15:0)  
RLen(7:0)  
VCC_OK  
Figure 20: Guard, Block, Wait and ATR Time Definitions  
1.7.15.4 Bypass Mode  
It is possible to bypass the smart card UART in order for the firmware to support non-T=0/T=1 smart cards.  
This is called Bypass mode. In this mode the embedded firmware will communicate directly with the  
selected smart card and drive I/O during transmit and read I/O during receive in order to communicate with  
the smart card. In this mode, ATR processing is under firmware control. The firmware must sequence the  
interface signals as required. Firmware must perform TS processing, parity checking, break generation and  
CRC/LRC calculation (if required).  
1.7.15.5 Synchronous Operation Mode  
The 73S1215F supports synchronous operation. When sync mode is selected for either interface, the CLK  
signal is generated by the ETU counter. The values in FDReg, SCCLK, and SCECLK must be set to obtain  
the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the interface must  
be selected to obtain a smart card clock signal. In sync mode, input data is sampled on the rise of CLK,  
and output data is changed on the fall of CLK.  
82  
Rev. 1.4  
 
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