DS_1215F_003
73S1215F Data Sheet
Smart card RST, I/O and CLK, C4, C8 shall be low before the end of the deactivation sequence. Figure
18 shows the timing for a deactivation sequence.
SELSC
bits
VCCSEL
bits
VCC
t4
VCCOK bit
RSTCRD bit
See Note
RST
CLK
ATR starts
IO
t1
t5
t4
t2
t3
tto
t1: SELSC.1 bit set (selects internal ICC interface) and a non-zero value in VCCSEL bits (calling for a
value of Vcc of 1.8, 3.0, or 5.0 volts) will begin the activation sequence. t1 is the time for Vcc to rise to
acceptable level, declared as Vcc OK (bit VCCOK gets set). This time depends on filter capacitor
value and card Icc load.
tto: The time allowed for Vcc to rise to Vcc OK status after setting of the VCCSEL bits. This time is
generated by the VCCTMR counter. If Vcc OK is not set, (bit VCCOK) at this time, a deactivation will
be initiated. VCCSEL bits are not automatically cleared. The firmware must clear the VCCSEL bits
before starting a new activation.
t2: Time from VCCTMR timeout and VCC OK to IO reception (high), typically 2-3 CLK cycles if
RDYST = 0. If RDYST = 1, t2 starts when VCCOK = 1.
t3: Time from IO = high to CLK start, typically 2-3 CLK cycles.
t4: Time allowed for start of CLK to de-assertion of RST. Programmable by RLength register.
t5: Time allowed for ATR timeout, set by the STSTO register.
Note: If the RSTCRD bit is set, RST is asserted (low). Upon clearing RSTCRD bit, RST will be
de-asserted after t4.
Figure 17: Asynchronous Activation Sequence Timing
Rev. 1.4
79
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
