73S1210F Data Sheet
DS_1210F_001
TX Control/Status Register (STXCtl): 0xFE06 0x00
This register is used to control transmission of data to the smart card. Some control and some status bits
are in this register.
Table 78: The STXCtl Register
MSB
LSB
I2CMODE
–
TXFULL TXEMTY TXUNDR LASTTX TX/RXB BREAKD
Bit
Symbol
Function
I2C Mode - When in sync mode and this bit is set, and when the RLen count
value = max or 0, the source of the smart card data for IO pin (or SIO pin) will
be connected to the IO bit in SCCtl (or SCECtl) register rather than the TX
FIFO. See the description for the Protocol Mode Register for more detail.
STXCtl.7
I2CMODE
–
STXCtl.6
STXCtl.5
TX FIFO is full. Additional writes may corrupt the contents of the FIFO. This
TXFULL bit it will remain set as long as the TX FIFO is full. Generates a TX_Event
interrupt upon going full.
1 = TX FIFO is empty, 0 = TX FIFO is not empty. If there is data in the TX
FIFO, the circuit will transmit it to the smart card if in transmit mode. In T=1
mode, if the LASTTX bit is set and the hardware is configured to transmit the
TXEMTY CRC/LRC, the TXEMTY will not be set until the CRC/LRC is transmitted. In
T=0, if the LASTTX bit is set, TXEMTY will be set after the last word has
been successfully transmitted to the smart card. Generates a TXEVNT
interrupt upon going empty.
STXCtl.4
TX Underrrun - (Read only) Asserted when a transmit under-run condition
has occurred. An under-run condition is defined as an empty TX FIFO when
the last data word has been successfully transmitted to the smart card and
the LASTTX bit was not set. No special processing is performed by the
hardware if this condition occurs. Cleared when read by firmware. This bit
generates a TXERR interrupt.
STXCtl.3
STXCtl.2
TXUNDR
Last TX Byte - Set by firmware (in both T=0 and T=1) when the last byte in
the current message has been written into the transmit FIFO. In T=1 mode,
the CRC/LRC will be appended to the message. Should be set after the last
LASTTX
byte has been written into the transmit FIFO. Should be cleared by firmware
before writing first byte of next message into the transmit FIFO. Used in T=0
to determine when to set TXEMTY.
1 = Transmit mode, 0 = Receive mode. Configures the hardware to be
receiving from or transmitting to the smart card. Determines which counters
should be enabled. This bit should be set to receive mode prior to switching
TX/RXB to another interface. Setting and resetting this bit shall initialize the CRC
logic. If LASTTX is set, this bit can be reset to RX mode and UART logic will
automatically change mode to RX when TX operation is completed
(TX_Empty = 1).
STXCtl.1
STXCtl.0
Break Detected - (Read only) 1 = A break has been detected on the I/O line
BREAKD indicating that the smart card detected a parity error. Cleared when read.
This bit generates a TXERR interrupt.
86
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
