DS_1210F_001
73S1210F Data Sheet
text
t0
PWRDN BIT
t1
PWRDN SIG
EXT. EVENT
t4
t6
INT0 to MPU
MPU STOP
t7
t2
ANALOG Enable
t3
t5
PLL CLOCKS
t0: MPU sets PWRDN bit.
t1: 32 MPU clock cycles after t0, the PWRDN SIG is asserted, turning all analog functions OFF.
t2: MPU executes STOP instruction, must be done prior to t1.
t3: Analog functions go to OFF condition. No Vref, PLL/VCO, Ibias, etc.
text: An external event (RTC, Keypad, Card event, USB) occurs.
t4: PWRDN bit and PWRDN signal are cleared by external event.
t5: High-speed oscillator/PLL/VCO operating.
t6: After 512 MPU clock cycles, INT0 to MPU is asserted.
t7: INT0 causes MPU to exit STOP condition.
Figure 8: Power Down Sequencing
Rev. 1.4
29
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
