DS_1210F_001
73S1210F Data Sheet
73S1210F will go into the “OFF” state (when VBUS is not present). If the ON/OFF switch function is not
desired and the application does not need to shut down power on VDD, the ON_OFF input can be
permanently grounded which will automatically turn on VDD when power is supplied on any of the VPC,
VBAT or VBUS power supply inputs.
If power is applied to both VBAT and VBUS, the circuit will automatically consume power from only the VBUS
source. The 73S1210F will be unconditionally “ON” when VBUS is applied. If the VBUS source is removed,
the 73S1210F will switchover to the VBAT input supply and remain in the “ON” state. The firmware
should assert SCPWRDN based on no activity or VBUS removal to reduce battery power consumption.
When operating from VBUS, and not calling for VCC, the step-up converter becomes a simple switch
connecting VBUS to VP in order to save power.
Note: When the ON_OFF switch function is not needed, i.e. when the 73S1210F must be in an always-ON
state when using another supply than VBUS (VPC or VBAT), some external discrete components are needed.
1.7.4 Power Control Modes
The 73S1210F contains circuitry to disable portions of the device and place it into a lower power standby
mode or power down the 73S1210F into its “OFF” mode. The standby mode will stop the core, clock
subsystem and the peripherals connected to it. This is accomplished by either shutting off the power or
disabling the clock going to the block. The Miscellaneous Control registers MISCtl0, MISCtl1 and the
Master Clock Control register (MCLKCtl) provide control over the power modes. The PWRDN bit in
MISCtl0 will setup the 73S1210F for standby or “OFF” modes. Depending on the state of the ON/OFF
circuitry and power applied to the VBUS input, the 73S1210F will go into either standby mode or power
“OFF” mode. If system power is provided by, VBUS or the ON/OFF circuitry is in the “ON” state, the MPU
core will placed into standby mode. If the VBUS input is not sourcing power and the ON/OFF circuitry is
in the “OFF” state, setting the PWRDN bit will shut down the converter and VP will turn off. The power
down mode should only be initiated by setting the PWRDN bit in the MISCtl0 register and not by
manipulating individual control bits in various registers. Figure 6 shows how the PWRDN bit controls the
various functions that comprise power down state.
Note: the PWRDN Signal is not the direct version of the PWRDN Bit. There are delays from assertion of the PWRDN
bit to the assertion of the PWRDN Signal (32 MPU clocks). Refer to the Power Down sequence diagram.
PWRDN Signal
MISCtl0 - PWRDN
Analog functions
(VCO, PLL,
reference and bias
circuits, etc.)
VDDFCtl - VDDFEN
VDDFAULT
+
ANALOG
COMPARE
ACOMP - CMPEN
+
High Speed OSC
+
MCLCKCtl - HOSEN
Smart Card Power
+
SCVCCCtl - SCPRDN
Flash Read Pulse
one-shot circuit
+
MISCtl1 - FRPEN
These are the block
references.
These are the registers and
the names of the control bits.
Figure 6: Power Down Control
Rev. 1.4
27
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
