73S1210F Data Sheet
DS_1210F_001
Pin Name
Description
RXTX
ERST
ISBR
43
38
3
27
23
IO
IO
IO
I
ICE control.
ICE control.
ICE control.
ICE control.
TCLK
ANA_IN
39
15
24
AI
Figure 38 Analog input pin. This signal goes to a programmable
comparator and is used to sense the value of an external
voltage.
SEC
2
I
Figure 37 Input pin for use in programming security fuse. It should be
connected to ground when not in use.
TEST
LED0
51
4
32
5
DI
IO
Figure 37 Test pin, should be connected to ground
Figure 36 Special output driver, programmable pull-down current to
drive LED. May also be used as an input.
VDD
N/C
68
28
40
3
16
25
PSO
VDD supply output pin. A 0.1µF capacitor is recommended
at each VDD pin.
7
8
No connect.
26
27
GND
9
2
8
15
26
GND
General ground supply pins for all IO and logic circuits.
25
42
67
RESET
1
4
I
Figure 32 Reset input, positive assertion. Resets logic and registers
to default condition. Note: to insure proper reset operation
after VDD is turned on by application of VBUS power or
activation of the ON/OFF switch, external reset circuitry
must generate a proper reset signal to the 73S1210F. This
can be accomplished via a simple RC network.
* See the figures in the Equivalent Circuits section.
10
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
