DS_1x66B_001
73M1866B/73M1966B Data Sheet
Pin
Pin Name
Type
Description
Number
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VND
INT
GND Negative digital ground
O
I
Interrupt / ring detect (active low – open drain)
SPI clock
SCLK
CS
I
SPI chip select (active low)
PCM transmit data sent to the D to A
Voltage regulator sense
I
DR
SRE
SRB
VBG
ACS
VNS
VPS
RXP
RXM
TXM
DCD
DCS
DCG
DCI
I
O
O
I
Voltage regulator drive
VBG bypass, connect to 0.1μF capacitor to VNS
AC current sense
GND Analog negative supply voltage
PWRO Analog positive supply voltage (output)
I
I
Receive plus – signal input
Receive minus – signal input
Transmit Minus – transhybrid cancellation output
DC loop output
O
O
I
DC loop current sense
O
I
DC loop control
DC loop input
I
Ring detect negative voltage input
Ring detect positive voltage input
Off-hook control
RGN
RGP
OFH
M20PB
VNX
SCP
MID
I
O
I
Test pin. Connect to VNX.
GND Negative supply voltage
I/O
I/O
Positive side of the secondary pulse transformer winding
Charge pump midpoint
PWR Supply from the barrier
VPX
2.6 Requisite Use of Exposed Bottom Pad on 73M1866B and 73M1966B QFN
Packages
The exposed bottom pad is not intended for thermal relief (heat dissipation) and should not be
soldered to the PCB. Soldering of the exposed pad could also compromise electrical
isolation/insulation requirements for proper voltage isolation. Avoid any PCB traces or through-hole
vias on the PCB beneath the exposed pad area.
Rev. 1.6
15
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
