73M1822/73M1922 Data Sheet
DS_1x22_017
Upon power up, the following sequence should be used to ensure barrier synchronization:
1. The Line-Side Device (73M1902) starts in Barrier Powered Mode and transmits a preamble to aid the
PLL locking of the
Line-Side Device.
2. When PLL Lock detect is achieved, the Line-Side Device transmits status data to the Host-Side Device.
3. When the Line-Side status Data is detected by the Host-Side Device, the barrier is considered to be in
synchronization by the Host-Side Device.
4. If the auto-poll mode is enabled, the Device ID is transmitted, which is followed by transmit data.
5. Upon detection of the Device ID, the Line-Side Device considers the Barrier to be in synchronization in
host-to-line side direction.
6. Line-Side Device starts sending Receive Data.
7. If the Auto-Poll bit is enabled, the Host-Side Device will have polled the Device ID of the Line-Side
Device. If the barrier is synchronized, then Register 0x1D[7:4], will be 1100. If not synchronized, then
0000.
10.4 Auxiliary A/D Converter
Line monitoring and sensing is performed with an 8-bit auxiliary A/D converter integrated in the
73M1922/73M1822. The input signals are connected to RGP and RGN pins. In certain applications, this
A/D can be used to sample signals unrelated to PSTN DAA functions. In this type of application, it is
necessary to isolate the input signal with optical or other means since the 73M1x22 is connected directly to
the PSTN and is susceptible to high voltage surge. Under normal conditions, RGP and RGN are AC
coupled to the line through high-voltage (250 V) capacitors.
10.5 Auto-Poll
Once the MSBI acquires synchronization, the MSBI state machine automatically sends a polling command
to the 73M1x12 LIC. More specifically, the Host-Side Device (73M1902) requests that the Line-Side Device
(73M1912) transmits its revision ID to the contents of Register 0x1D[7:4] in the 73M1902. The “revision ID”
part of that specific register is cleared upon power up or upon loss of synchronization. After this auto-poll
sequence, the host should read Register 0x1D[7:4] and determine if the “revision ID” field is all zeros or not.
If it is not all zeros, this implies synchronization is established between the Host-Side Device and Line-Side
Device.
The auto-poll mechanism can be disabled by setting the ENAPOL bit (Register 0x05[3]).
58
Rev. 1.6
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
