DS_1x22_017
73M1822/73M1922 Data Sheet
10 Barrier Information
10.1 Isolation Barrier
The 73M1x22 uses the Teridian MicroDAA proprietary isolation method based upon low cost pulse
transformer coupling. This technique provides several advantages over other methods, including lower
BOM cost, reduced component count, and significantly enhances common mode noise immunity, lower
radiated noise (EMI), and improved operation in noisy environments. The MicroDAA technology has
additional and enhanced functionality such as the support of powering the Line-Side DAA circuit from the
Host-Side Device. This allows operation on leased lines circuits and on low current conditions commonly
encountered in long loops. The MicroDAA can also operate entirely from line power when sufficient loop
current is available.
Since the transformer is the only component crossing the isolation barrier, it solely determines the isolation
between the PSTN and the 73M1x22 digital interface. Several vendors can supply compatible transformers
with ratings up to 6000 V.
10.2 Barrier Powered Options
The 73M1x22 has the ability to be used either in a Line Powered Mode or one where the Line-Side Device
can be powered across the barrier from the Host-Side Device. The power on default for the 73M1x22 is
Barrier Powered Mode.
10.2.1 Barrier Powered Operation
In this default mode of operation the 73M1x22 Host-Side Device drives the pulse transformer in such a way
that power pulses are time division multiplexed into the transmit bit stream (half the time) that is rectified by
circuitry in the Line-Side Device and uses this energy to power itself.
10.2.2 Line Powered Operations
If there is sufficient current available from the PSTN line, the 73M1x22 can be programmed to use line
power instead of across the barrier.
10.3 Synchronization of the Barrier
Since the communication across the barrier is digital, synchronization of data across the barrier is of
absolute importance. To that end, the devices implement special procedures to ensure reliability across the
barrier.
When loss of synchronization is detected, the SLHS bit is set to 1 and likewise SYNL is also set to 1 and
initiates an interrupt to the host. Once the SYNL bit is asserted a new barrier synchronization sequence will
automatically begin.
Once read, the SLHS bit is reset, but will be set again if the synchronization loss continues.
Rev. 1.6
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TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
