73K324BL
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
CONTROL REGISTER 2
D7
0
D6
D5
D4
D3
D2
D1
D0
CR2
100
SPEC
REG
CALL
INIT
TRANSMIT
S1
16 WAY
RESET
DSP
TRAIN
INHIBIT
EQUALIZER
ENABLE
ACCESS
BIT
NAME
CONDITION
DESCRIPTION
D0
Equalizer
Enable
0
1
The adaptive equalizer is in its initialized state.
The adaptive equalizer is enabled. This bit is used in
handshakes to control when the equalizer should
calculate its coefficients.
D1
D2
Train Inhibit
0
1
The adaptive equalizer is active.
The adaptive equalizer coefficients are frozen.
RESET DSP
0
1
The DSP is inactive and all variables are initialized.
The DSP is running based on the mode set by other
control bits.
D3
D4
16 Way
0
1
The receiver and transmitter are using the same decision
plane (based on the modulator control mode).
The receiver, independent of the transmitter, is forced
into a 16 point decision plane. Used for QAM
handshaking.
Transmit S1
0
1
The transmitter when placed in alternating mark/space
mode transmits 0101...... scrambled or not dependent on
the bypass scrambler bit.
When this bit is 1 and only when the transmitter is placed
in alternating mark/space mode by CR1 bits D7, D6, and
in DPSK or QAM, an unscrambled repetitive double di-bit
pattern of 00 and 11 at 1200 bps (S1) is sent
D5
Call Init
Special
0
1
The DSP is set-up to do demodulation and pattern
detection based on the various mode bits. Both answer
tones are detected in demodulation mode concurrently;
TR-D0 is ignored.
The DSP decodes unscrambled mark, answer tone and
call progress tones.
D6
D7
0
1
Normal CR3 access.
Register
Access
Setting this bit and addressing CR3 allows access to the
special register (see the special register for details).
Not used at this time
0
Only write zero to this bit.
Page: 17 of 34
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
