73K222BL
V.22, V.21, Bell 212A, 103 Single-Chip
Modem with Integrated Hybrid
DATA SHEET
DTE USER
NAME
EXCLK
PIN
22
TYPE
I
DESCRIPTION
External Clock. This signal is used in synchronous transmission when the
external timing option has been selected. In the external timing mode the
rising edge of EXCLK is used to strobe synchronous DPSK transmit data
applied to on the TXD pin. Also used for serial control interface.
Receive Clock. The falling edge of this clock output is coincident with the
transitions in the serial received data output. The rising edge of RXCLK
can be used to latch the valid output data. RXCLK will be valid as long as
a carrier is present.
Received Data Output. Serial receive data is available on this pin. The
data is always valid on the rising edge of RXCLK when in synchronous
mode. RXD will output constant marks if no carrier is detected.
Transmit Clock. This signal is used in synchronous transmission to latch
serial input data on the TXD pin. Data must be provided so that valid data
is available on the rising edge of the TXCLK. The transmit clock is derived
from different sources depending upon the synchronization mode
selection. In internal mode the clock is generated internally. In external
mode TXCLK is phase locked to the EXCLK pin. In slave mode TXCLK is
phase locked to the RXCLK pin. TXCLK is always active.
Transmit Data Input. Serial data for transmission is applied on this pin.
In synchronous modes, the data must be valid on the rising edge of the
TXCLK clock. In asynchronous modes (1200/600 bit/s or 300 baud) no
clocking is necessary. DPSK data must be 1200/600 bit/s +1%, -2.5%
or +2.3%, -2.5 % in extended over speed mode.
RXCLK
26
O
RXD
25
O/
Weak
Pull-up
O
TXCLK
21
TXD
24
I
ANALOG INTERFACE AND OSCILLATOR
NAME
RXA
TXA1
TXA2
XTL1
XTL2
PIN
32
18
17
3
4
TYPE
I
O
I
I
DESCRIPTION
Received modulated analog signal input from the telephone line
interface.
Transmit analog output to the telephone line interface.
These pins are for the internal crystal oscillator requiring an 11.0592
MHz parallel mode crystal. Load capacitors should be connected from
XTL1 and XTL2 to ground. XTL2 can also be driven from an external
clock.
Off-hook relay driver. This signal is an open drain output capable of
sinking 40 mA and is used for controlling a relay. The output is the
complement of the OH register bit in the ID Register.
OH
27
O
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©
2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
