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73K222BL-IHR/F 参数 Datasheet PDF下载

73K222BL-IHR/F图片预览
型号: 73K222BL-IHR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片调制解调器 [Single-Chip Modem]
分类和应用: 调制解调器
文件页数/大小: 26 页 / 168 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
 浏览型号73K222BL-IHR/F的Datasheet PDF文件第6页浏览型号73K222BL-IHR/F的Datasheet PDF文件第7页浏览型号73K222BL-IHR/F的Datasheet PDF文件第8页浏览型号73K222BL-IHR/F的Datasheet PDF文件第9页浏览型号73K222BL-IHR/F的Datasheet PDF文件第11页浏览型号73K222BL-IHR/F的Datasheet PDF文件第12页浏览型号73K222BL-IHR/F的Datasheet PDF文件第13页浏览型号73K222BL-IHR/F的Datasheet PDF文件第14页  
73K222BL  
V.22, V.21, Bell 212A, 103 Single-Chip  
Modem with Integrated Hybrid  
DATA SHEET  
CONTROL REGISTER 0 (continued)  
D7  
D6  
D5  
TRANSMIT TRANSMIT  
MODE 3 MODE 2  
D4  
D3  
D2  
D1  
D0  
CR0  
000  
MODUL.  
OPTION  
0
TRANSMIT  
MODE 1  
TRANSMIT  
MODE 0  
TRANSMIT  
ENABLE  
ANSWER/  
ORIGINATE  
BIT NO.  
NAME  
CONDITION  
D7 D5 D4  
DESCRIPTION  
Selects:  
0
1
0
1
0
0
1
1
X
X
1
1
DPSK mode at 1200 bit/s.  
DPSK mode at 600 bit/s.  
FSK Bell 103 mode.  
FSK CCITT V.21 mode.  
X = Don’t care  
D7  
Modulation  
Option  
CONTROL REGISTER 1  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
CR1  
001  
TRANSMIT TRANSMIT  
ENABLE  
DETECT  
INTER.  
BYPASS  
SCRAMB  
CLK  
TEST  
MODE  
1
TEST  
MODE  
0
PATTERN  
1
PATTERN  
0
CONTROL  
RESET  
BIT NO.  
NAME  
Test Mode  
CONDITION  
DESCRIPTION  
Selects normal operating mode  
D1, D0  
D1  
0
D0  
0
0
1
Analog loopback mode. Loops the transmitted analog  
signal back to the receiver, and causes the receiver to  
use the same center frequency as the transmitter. To  
squelch the TXA pin, transmit enable must be forced  
low.  
1
1
0
1
Selects remote digital loopback. Received data is  
looped back to transmit data internally, and RXD is  
forced to a mark. Data on TXD is ignored.  
Selects local digital loopback. Internally loops TXD  
back to RXD and continues to transmit carrier from  
TXA pin.  
D2  
D3  
Reset  
0
1
Selects normal operation.  
Resets modem to power-down state. All  
control register bits (CR0, CR1, TONE) are reset to  
zero. The output of the CLK pin will be set to the  
crystal frequency. This bit clears itself.  
CLK Control  
(Clock Control)  
0
1
Selects 11.0592 MHz crystal echo output at CLK pin.  
Selects 16 times the data rate, output at CLK pin in  
DPSK modes only.  
Page: 10 of 26  
© 2005, 2008 TERIDIAN Semiconductor Corporation  
Rev 7.2