FDS 6531/6532 005
Interrupt Enable
Data Sheet 71M6531D/F-71M6532D/F
Interrupt Flag
Name Location
SFR C0[3]
Interrupt Description
Name
Location
SFR B8[3]
SFR B8[4]
SFR B8[5]
2002[0]
EX4
EX5
EX6
IEX4
IEX5
IEX6
External interrupt 4
SFR C0[4]
SFR C0[5]
SFR E8[0]
SFR E8[1]
External interrupt 5
External interrupt 6
EX_XFER
EX_RTC
IE_XFER
IE_RTC
XFER_BUSY interrupt (INT 6)
RTC_1SEC interrupt (INT 6)
WDT near overflow (INT 6)
SPI Interface (INT2)
2002[1]
IEN_WD_NROVF 20B0[0]
WD_NROVF_FLAG 20B1[0]
IEN_SPI
20B0[4]
SPI_FLAG
IE_FWCOL0
IE_FWCOL1
IE_PLLRISE
IE_PLLFALL
IE_WAKE
20B1[4]
SFR E8[3]
SFR E8[2]
SFR E8[6]
SFR E8[7]
SFR E8[5]
SFR E8[4]
FWCOL0 interrupt (INT 2)
FWCOL1 interrupt (INT 2)
PLL_OK rise interrupt (INT 4)
PLL_OK fall interrupt (INT 4)
AUTOWAKE flag†
EX_FWCOL
2007[4]
EX_PLL
2007[5]
IE_PB
PB flag†
† The AUTOWAKE and PB flag bits are shown in Table 31 because they behave similarly to interrupt flags,
even though they are not actually related to an interrupt. These bits are set by hardware when the MPU
wakes from a push button or wake timeout. The bits are reset by writing a zero. Note that the PB flag is
set whenever the PB is pushed, even if the part is already awake.
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 32:
Table 32: Interrupt Priority Level Groups
Group
Group Members
0
1
2
3
4
5
External interrupt 0, Serial channel 1 interrupt
Timer 0 interrupt, External interrupt 2
External interrupt 1, External interrupt 3
Timer 1 interrupt, External interrupt 4
Serial channel 0 interrupt, External interrupt 5
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 33) by setting or clearing one bit in the SFR interrupt priority register IP0 and one in IP1 (Table 34).
If requests of the same priority level are received simultaneously, an internal polling sequence as shown
in Table 35 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 33: Interrupt Priority Levels
IP1[x]
IP0[x]
Priority Level
Level 0 (lowest)
Level 1
0
0
1
1
0
1
0
1
Level 2
Level 3 (highest)
v1.3
© 2005-2010 TERIDIAN Semiconductor Corporation
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