Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
For example, PRE_SAMPS[1:0] = 42 and SUM_CYCLES[5:0] = 50 will establish 2100 samples per accumulation
cycle. PRE_SAMPS[1:0] = 100 and SUM_CYCLES[5:0] = 21 will result in the exact same accumulation
cycle of 2100 samples or 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt
signals to the MPU that accumulated data are available.
1/32768Hz =
30.518µs
IB
VB
IA
VA
13/32768Hz = 397µs
per mux cycle
Figure 6: Samples from Multiplexer Cycle
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle status information, such as sag data and the digitized input signal, is available to the MPU.
833ms
20ms
XFER_BUSY
Interrupt to MPU
Figure 7: Accumulation Interval
Figure 7 shows the accumulation interval resulting from PRE_SAMPS[1:0] = 42 and SUM_CYCLES[5:0] =
50, consisting of 2100 samples of 397 µs each, followed by the XFER_BUSY interrupt. The sampling in
this example is applied to a 50 Hz signal.
There is no correlation between the line signal frequency and the choice of PRE_SAMPS[1:0] or
SUM_CYCLES[5:0] (even though when SUM_CYCLES[5:0] = 42 one set of SUM_CYCLES[5:0] happens to
sample a period of 16.6 ms). Furthermore, sampling does not have to start when the line voltage crosses
the zero line and the length of the accumulation interval need not be an integer multiple of the signal cycles.
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