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71M6531D_10 参数 Datasheet PDF下载

71M6531D_10图片预览
型号: 71M6531D_10
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 120 页 / 1966 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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Data Sheet 71M6531D/F-71M6532D/F  
FDS 6531/6532 005  
1.3.1 Meter Equations  
The 71M6531D/F and 71M6532D/F provide hardware assistance to the CE in order to support various  
meter equations. This assistance is controlled through I/O RAM location EQU[2:0] (equation assist). The  
Compute Engine (CE) firmware for residential configurations implements the equations listed in Table 5.  
EQU[2:0] specifies the equation to be used based on the number of phases used for metering.  
Table 5: Meter Equations  
Watt and VAR Formula  
Mux  
Sequence  
ALT Mux  
Sequence  
EQU[2:0]  
Description  
Element Element Element  
0
1
2
1 element, 2 W,  
1φ with neutral  
current sense  
0
VA · IA  
VA · IB  
N/A  
Sequence is  
programmable  
with  
Sequence is  
programmable with  
SLOTn_ALTSEL[3:0]  
1 element, 3 W,  
1φ  
VA(IA-  
IB)/2  
1
2
N/A  
N/A  
N/A  
SLOTn_SEL[3:0]  
2 element, 3 W,  
3φ Delta  
VA · IA  
VB · IB  
Not all CE codes support all equations.  
1.3.2 Real-Time Monitor  
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM  
locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the  
digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled  
with the RTM_E bit. The RTM output is clocked by CKTEST (pin SEG19/CKTEST), with the clock output  
enabled by setting CKOUT_E = 1. Each RTM word is clocked out in 35 cycles and contains a leading flag  
bit. See Figure 20 for the RTM output format. RTM is low when not in use.  
1.3.3 Pulse Generators  
The 71M6531D/F and 71M6532D/F provide four pulse generators, RPULSE, WPULSE, XPULSE and  
YPULSE, as well as increased hardware support for the two original pulse generators (RPULSE and  
WPULSE). The pulse generators can be used to output CE status indicators, SAG for example, to DIO pins.  
The polarity of the pulses may be inverted with the PLS_INV bit. When this bit is set, the pulses are active  
high, rather than the more usual active low. PLS_INV inverts all the pulse outputs.  
XPULSE and YPULSE  
Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse outputs. Pins DIO8  
and DIO9 are used for these pulses. Generally, the XPULSE and YPULSE outputs are updated once on  
each pass of the CE code, resulting in a pulse frequency up to a maximum of 1260Hz (assuming a MUX  
frame is 13 CK32 cycles).  
The YPULSE pin can be used by the CE code to generate interrupts based on sag events. This method  
is faster than checking the sag bits by the MPU at every CE_BUSY interrupt. See Section 4.3.6 CE Status  
and Control for details.  
RPULSE and WPULSE  
During each CE code pass, the hardware stores exported WPULSE AND RPULSE sign bits in an 8-bit  
FIFO and outputs them at a specified interval. This permits the CE code to calculate the RPULSE and  
WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them over the MUX  
frame. The FIFO is reset at the beginning of each MUX frame. The PLS_INTERVAL register controls the  
delay to the first pulse update and the interval between subsequent updates. Its LSB is 4 CK_FIR cycles.  
If zero, the FIFO is deactivated and the DFFs are updated immediately. Thus, NINTERVAL is  
4 * PLS_INTERVAL.  
16  
© 2005-2010 TERIDIAN Semiconductor Corporation  
v1.3