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71M6515H-IGTW1 参数 Datasheet PDF下载

71M6515H-IGTW1图片预览
型号: 71M6515H-IGTW1
PDF下载: 下载PDF文件 查看货源
内容描述: 截至10ppmC精密超稳定的电压基准数字温度补偿 [Up to 10ppmC precision ultra-stable voltage reference Digital temperature compensation]
分类和应用: 温度补偿
文件页数/大小: 60 页 / 827 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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71M6515H  
A Maxim Integrated Products Brand  
Energy Meter IC  
DATA SHEET  
JULY 2011  
Element Output Mapping  
Watt & VAR Formula  
EQU  
W0SUM/  
VAR0SUM  
W1SUM/  
W2SUM/  
I0SQ  
SUM  
I1SQ  
SUM  
I2SQ  
SUM  
(WSUM/VARSUM)  
VAR1SUM  
VAR2SUM  
0
1
VA*IA  
-
-
IA  
-
-
VA IA (1 element, 2W 1φ)  
VA*(IA-IB)/2  
(1 element, 3W 1φ)  
VA*(IA-IB)/2  
VA*IA  
VA*IB  
-
IA-IB  
IB  
-
VA*IA + VB*IB  
(2 element, 3W 3φ Delta)  
2
3
VB*IB  
-
-
IA  
IA-IB  
IA-IB  
IA  
IB  
IB  
-
VA*(IA-IB)/2 + VC*IC  
(2 element, 4W 3φ Delta)  
VA*(IA-IB)/2  
VC*IC  
IC  
IC  
IC  
4
5
VA*(IA-IB)/2 + VB*(IC-IB)/2  
(2 element, 4W 3φ Wye)  
VA*(IA-IB)/2 VB*(IC-IB)/2  
VA*IA VB*IB  
IC-IB  
IB  
VA*IA + VB*IB + VC*IC  
(3 element, 4W 3φ Wye)  
VC*IC  
Table 2: Meter Element Output Mapping  
ANALOG FRONT END  
A/D Converter (ADC)  
A single delta-sigma A/D converter (ADC) digitizes the inputs to the device. The resolution of the ADC is 21 bits. The ADC  
operates at 5MHz oversampling rate and places the digital results in CE memory. Each analog input is sampled at 2520Hz.  
Once each accumulation interval, it refreshes the temperature value that is placed in the TEMP_RAW register. The analog re-  
ference for all inputs is V3P3A, i.e. the ADC processes voltages between the input pins and V3P3A.  
Voltage Reference  
The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques as well as  
production trims to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable  
temperature coefficient.  
The CE compensates for temperature characteristics of the voltage reference by modifying the gain applied to the V and I  
channels based on the coefficients PPMC and PPMC2. See the section “TEMPERATURE COMPENSATION” for details.  
DIGITAL COMPUTATION  
The six ADC outputs are processed and accumulated digitally. The default product summation is based on 42*60 (if the  
SUM_CYCLES register is set to 60) samples per accumulation interval. At the end of each accumulation interval, a ready  
interrupt (IRQZ) is signaled (if enabled with the READY bit in STMASK), indicating that fresh data is available to the host. For  
instance, if SUM_CYCLES =30, the IRQZ rate will be 2Hz (500ms).  
A dedicated 32-bit Computation Engine (CE) performs the precision computations necessary to accurately measure energy.  
Internal CE calculations include frequency-insensitive offset cancellation on all six channels and a frequency insensitive 90°  
phase shifter for VAR calculations. The CE also includes LPF smoothing filters after each product and squaring circuit to  
attenuate ripple and eliminate beat frequencies between the power line fundamental and the accumulation time. The CE  
directly calculates Watts, VARs, V2, and I2 and accumulates them for one interval.  
At the end of each CE computation cycle, the accumulated data are post-processed to calculate RMS amplitudes, phase  
angles, and VAh. When post-processing is complete, the IRQZ signal is activated.  
Page: 16 of 60  
© 20052011 Teridian Semiconductor Corporation  
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