欢迎访问ic37.com |
会员登录 免费注册
发布采购

71M6533H-IGT/F 参数 Datasheet PDF下载

71M6533H-IGT/F图片预览
型号: 71M6533H-IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用: 模拟IC信号电路
文件页数/大小: 124 页 / 1997 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
 浏览型号71M6533H-IGT/F的Datasheet PDF文件第90页浏览型号71M6533H-IGT/F的Datasheet PDF文件第91页浏览型号71M6533H-IGT/F的Datasheet PDF文件第92页浏览型号71M6533H-IGT/F的Datasheet PDF文件第93页浏览型号71M6533H-IGT/F的Datasheet PDF文件第95页浏览型号71M6533H-IGT/F的Datasheet PDF文件第96页浏览型号71M6533H-IGT/F的Datasheet PDF文件第97页浏览型号71M6533H-IGT/F的Datasheet PDF文件第98页  
71M6533/71M6534 Data Sheet  
FDS_6533_6534_004  
The EXT_TEMP bit enables temperature compensation by the MPU, when set to 1. When 0, internal (CE)  
temperature compensation is enabled.  
I0_SHUNT, I1_SHUNT and I2_SHUNT can configure their respective current inputs to accept shunt resistor  
sensors. In this case the CE provides an additional gain of 8 to the selected current input. WRATE may  
need to be adjusted based on the values In_SHUNT.  
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by  
the MPU if EXT_PULSE = 1. In this case, the MPU controls the pulse rate by placing values into APULSEW  
and APULSER. By setting EXT_PULSE = 0, the CE controls the pulse rate based on WSUM and VARSUM.  
The 71M6533 Demo Code creep function halts both internal and external pulse generation.  
Table 53: CECONFIG Bit Definitions  
CECONFIG  
Name  
Default Description  
[bit]  
[20]  
[19]  
[18]  
[17]  
SAG_MASK2  
SAG_MASK1  
SAG_MASK0  
SAG_INT  
0
0
0
0
When 1, enables sag interrupt based on phase C.  
When 1, enables sag interrupt based on phase B.  
When 1, enables sag interrupt based on phase A.  
When 1, activates YPULSE/DIO8 output when a sag is de-  
tected (see also 1.4.7).  
EXT_TEMP  
SAG_CNT  
[16]  
0
When 1, enables temperature compensation by the MPU.  
When 0, internal (CE) temperature compensation is enabled.  
[15:8]  
80  
The number of consecutive voltage samples below SAG_THR  
(0x50) before a sag alarm is declared. The maximum value is 255.  
SAG_THR is at address 0x24.  
FREQSEL1  
FREQSEL0  
[7]  
[6]  
0
The combination of FREQSEL1 and FEQSEL2 selects the  
phase to be used for the frequency monitor, the phase-to-  
phase lag calculation and for the zero crossing counter  
(MAINEDGE_X).  
FREQ FREQ Phase  
Phases Used for Voltage  
Phase Lag Calculation  
0
SEL1  
SEL0  
Se-  
lected  
PH_AtoB_X  
A-B  
PH_AtoC_X  
A-C  
0
0
1
1
0
1
0
1
A
B
C
B-C  
B-A  
C-A  
C-B  
Not allowed  
EXT_PULSE  
IC_SHUNT  
[5]  
[4]  
1
0
When zero, causes the pulse generators to respond to internal  
data (WPULSE = WSUM_X, RPULSE = VARSUM_X,  
XPULSE = WSUM_X). Otherwise, the generators respond to  
values the MPU places in APULSEW and APULSER.  
When 1, the current gain of channel C is increased by 8. The  
gain factor controlled by In_SHUNT is referred to as In_8  
throughout this document.  
IB_SHUNT  
IA_SHUNT  
[3]  
[2]  
[1]  
0
0
0
When 1, the current gain of channel B is increased by 8.  
When 1, the current gain of channel A is increased by 8.  
PULSE_FAST  
When PULSE_FAST = 1, the pulse generator input is increased  
16x. When PULSE_SLOW = 1, the pulse generator input is  
reduced by a factor of 64. These two parameters control the  
pulse gain factor X (see table below). Allowed values are ei-  
94  
© 2007-2009 TERIDIAN Semiconductor Corporation  
v1.1