71M6533/71M6534 Data Sheet
FDS_6533_6534_004
4.3.4 Environment
Before starting the CE using the CE_E bit, the MPU has to establish the proper environment for the CE by
implementing the following steps:
•
•
•
•
•
•
Load the CE data into RAM.
Establish the equation to be applied in EQU.
Establish the accumulation period and number of samples in PRE_SAMPS and SUM_CYCLES.
Establish the number of cycles per ADC multiplexer frame (MUX_DIV).
Apply proper values to SLOTn_SEL and SLOTn_ALTSEL.
Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or a power failure detection interrupt.
Typically, there are thirteen 32768 Hz cycles per ADC multiplexer frame (see Figure 18 in the System
Timing Summary section). This means that the product of the number of cycles per frame and the num-
ber of conversions per frame must be 12 (allowing for one settling cycle). The default configuration is
FIR_LEN = 0 (two cycles per conversion) and MUX_DIV = 6 (6 conversions per mux cycle).
4.3.5 CE Calculations
Table 48: CE EQU Equations and Element Input Mapping
Watt & VAR Formula
(WSUM/VARSUM)
EQU
W0SUM/
W1SUM/
W2SUM/
I0SQ
SUM
I1SQ
SUM
I2SQ
SUM
VAR0SUM VAR1SUM VAR2SUM
VA IA
(1 element, 2W 1φ)
0*
1*
2*
3*
4*
5
VA*IA
VA*(IA-IB)/2
VA*IA
–
–
–
IA
IA-IB
IA
–
IB
–
–
VA*(IA-IB)/2
(1 element, 3W 1φ)
–
–
VA*IA + VB*IB
(2 element, 3W 3φ Delta)
VB*IB
–
IB
–
VA*(IA-IB)/2 + VC*IC
(2 element, 4W 3φ Delta)
VA*(IA-IB)/2
VC*IC
–
IA-IB
IA-IB
IA
IB
IC
IC
IC
VA*(IA-IB)/2 + VB*(IC-IB)/2
(2 element, 4W 3φ Wye)
VA*(IA-IB)/2 VB*(IC-IB)/2
VA*IA VB*IB
IC-IB
IB
VA*IA + VB*IB + VC*IC
(3 element, 4W 3φ Wye)
VC*IC
* Only EQU = 5 is supported by CE code version CE34A02D.
4.3.6 CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by reading addresses 0 through B shown in
Table 49.
Table 49: CE Raw Data Access Locations
Address
Name
IA FIR data
Description
CE
MPU
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
Type
Input
Input
Input
Input
Input
Input
Input
0x00
0x01
0x02
0x03
0x04
0x05
0x06
VA FIR data
IB FIR data
VB FIR data
IC FIR data
VC FIR data
ID FIR data
ADC Input data, valid at the end of the
MUX frame. The address mapping of ana-
log inputs to memory is hard-wired in the
ADC converter circuit.
92
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