71M6533/71M6534 Data Sheet
FDS_6533_6534_004
Timer/Counter 0
If set, enables external gate control (signal INT0). When INT0 is high,
TMOD[3]
Gate
and the TR0 bit is set (see the TCON register), a counter is incremented
every falling edge on T0 input signal.
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as
a timer.
TMOD[2]
C/T
TMOD[1:0] M1:M0
Selects the mode for Timer/Counter 0, as shown in Table 20.
Table 23: The TCON Register Bit Functions (SFR 0x88)
Bit
Symbol
Function
TCON[7]
TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when
an interrupt is processed.
TCON[6]
TCON[5]
TR1
TF0
Timer 1 run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag set by hardware when Timer 0 overflows. This
flag can be cleared by software and is automatically cleared when an
interrupt is processed.
TCON[4]
TCON[3]
TR0
IE1
Timer 0 Run control bit. If cleared, Timer 0 stops.
Interrupt 1 edge flag is set by hardware when the falling edge on exter-
nal pin int1 is observed. Cleared when an interrupt is processed.
TCON[2]
TCON[1]
TCON[0]
IT1
IE0
IT0
Interrupt 1 type control bit set by the MPU. Selects either the falling
edge or low level on input pin to cause an external interrupt.
Interrupt 0 edge flag is set by hardware when the falling edge on exter-
nal pin int0 is observed. Cleared when an interrupt is processed.
Interrupt 0 type control bit. Selects either the falling edge or low level
on input pin to cause interrupt.
1.3.8 WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard watchdog timer instead (see Section
1.4.12 Hardware Watchdog Timer).
1.3.9 Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s)
located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the corres-
ponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and IEN2.
Figure 7 shows the device interrupt structure.
Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 36. Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt ser-
vice is terminated by a return from instruction, RETI. When an RETI is performed, the processor will re-
turn to the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is
set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the in-
terrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the fol-
lowing conditions are met:
•
•
•
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
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