FDS_6533_6534_004
71M6533/71M6534 Data Sheet
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
•
•
•
•
The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 24, Table 25 and Table 26).
The Timer/Counter control registers, TCON and T2CON (see Table 27 and Table 28).
The interrupt request register, IRCON (see Table 29).
The interrupt priority registers: IP0 and IP1 (see Table 34).
Table 24: The IEN0 Bit Functions (SFR 0xA8)
Bit
Symbol Function
IEN0[7]
IEN0[6]
IEN0[5]
IEN0[4]
IEN0[3]
IEN0[2]
IEN0[1]
IEN0[0]
EAL
WDT
–
EAL = 0 disables all interrupts.
Not used for interrupt control.
Not Used.
ES0
ET1
EX1
ET0
EX0
ES0 = 0 disables serial channel 0 interrupt.
ET1 = 0 disables timer 1 overflow interrupt.
EX1 = 0 disables external interrupt 1.
ET0 = 0 disables timer 0 overflow interrupt.
EX0 = 0 disables external interrupt 0.
Table 25: The IEN1 Bit Functions (SFR 0xB8)
Bit
Symbol Function
IEN1[7]
IEN1[6]
IEN1[5]
IEN1[4]
IEN1[3]
IEN1[2]
IEN1[1]
IEN1[0]
–
Not used.
–
Not used.
EX6
EX5
EX4
EX3
EX2
–
EX6 = 0 disables external interrupt 6.
EX5 = 0 disables external interrupt 5.
EX4 = 0 disables external interrupt 4.
EX3 = 0 disables external interrupt 3.
EX2 = 0 disables external interrupt 2.
Not Used.
Table 26: The IEN2 Bit Functions (SFR 0x9A)
Bit
Symbol Function
ES1
ES1 = 0 disables the serial channel 1 interrupt.
IEN2[0]
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
31
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
