71M6521DE/71M6521FE
Energy Meter IC
DATASHEET
JANUARY 2008
LCD interface memory is powered by the non-volatile supply. The bits of the LCD memory are preserved in
LCD and SLEEP modes, even if their pin is not configured as SEG. In this case, they can be useful as general-
purpose non-volatile storage.
Battery Monitor
The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure Enable) bit is set.
While BME is set, an on-chip 45kΩ load resistor is applied to the battery and a scaled fraction of the battery voltage is applied
to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at CE DRAM address 0x07.
BME is ignored and assumed zero when system power is not available. See the Battery Monitor section of the Electrical
Specification section for details regarding the ADC LSB size and the conversion accuracy.
EEPROM Interface
The 71M6521DE/FE provides hardware support for either type of EEPROM interface, a two-pin interface and a three-pin
interface. The interfaces use the EECTRL and EEDATA registers for communication.
Two-Pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto pins
DIO4 (SCK) and DIO5 (SDA) controlled by the DIO_EEX bit I/O RAM (see I/O RAM Table). The MPU communicates with the
interface through two SFR registers: EEDATA and EECTRL. If the MPU wishes to write a byte of data to EEPROM, it places the
data in EEDATA and then writes the ‘Transmit’ command (CMD = 0011) to EECTRL. This initiates the transmit operation. The
transmit operation is finished when the BUSY bit falls. Interrupt INT5 is also asserted when BUSY falls. The MPU can then
check the RX_ACK bit to see if the EEPROM acknowledged the transmission.
A byte is read by writing the ‘Receive’ command (CMD = 0001) to EECTRL and waiting for the BUSY bit to fall. Upon comple-
tion, the received data is in EEDATA. The serial transmit and receive clock is 78kHz during each transmission, and the clock is
held in a high state until the next transmission. The bits in EECTRL are shown in Table 57.
The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly (“bit-banging”). However, con-
trolling DIO4 and DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too
busy to process interrupts.
Status
Bit
Read/
Write
Reset
State
Name
Polarity
Description
7
6
5
4
ERROR
BUSY
R
R
R
R
0
0
1
1
Positive
Positive
1 when an illegal command is received.
1 when serial data bus is busy.
RX_ACK
TX_ACK
Negative 0 indicates that the EEPROM sent an ACK bit.
Negative 0 indicates when an ACK bit has been sent to the EEPROM
CMD
Operation
0000
No-op. Applying the no-op command will stop the I2C clock
(SCK, DIO4). Failure to issue the no-op command will keep
the SCK signal toggling.
0001
0011
0101
Receive a byte from EEPROM and send ACK.
Transmit a byte to EEPROM.
Positive,
see CMD
Table
CMD[3:0
]
3-0
W
0
Issue a ‘STOP’ sequence.
0110
1001
Receive the last byte from EEPROM, do not send ACK.
Issue a ‘START’ sequence.
Others No Operation, set the ERROR bit.
Table 57: EECTRL Status Bits
Page: 42 of 101
© 2005-2008 TERIDIAN Semiconductor Corporation
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