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71M6521BE-IGTR/F 参数 Datasheet PDF下载

71M6521BE-IGTR/F图片预览
型号: 71M6521BE-IGTR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 97 页 / 1586 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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71M6521BE  
Energy Meter IC  
DATA SHEET  
JANUARY 2008  
Table 23 specifies the combinations of operation modes allowed for timer 0 and timer 1:  
Timer 1  
Mode 0  
YES  
Mode 1  
YES  
Mode 2  
YES  
Timer 0 - mode 0  
Timer 0 - mode 1  
Timer 0 - mode 2  
YES  
YES  
YES  
Not allowed  
Not allowed  
YES  
Table 23: Timer Modes  
Timer/Counter Mode Control register (PCON):  
MSB  
LSB  
SMOD  
--  
--  
--  
--  
--  
--  
--  
Table 24: The PCON Register  
The SMOD bit in the PCON register doubles the baud rate when set.  
Bit  
Symbol  
Function  
PCON.7  
SMOD  
Table 25: PCON Register Bit Description  
WD Timer (Software Watchdog Timer)  
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset, the  
watchdog timer is disabled and all registers are set to zero. The watchdog consists of a 16-bit counter (WDT), a reload register  
(WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog is started, it cannot be stopped unless the  
internal reset signal becomes active.  
Note: It is recommended to use the hardware watchdog timer instead of the software watchdog timer.  
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register enters the state 0x7CFF,  
an asynchronous WDTS signal will become active. The signal WDTS sets bit 6 in the IP0 register and requests a reset state.  
WDTS is cleared either by the reset signal or by changing the state of the WDT timer.  
Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming  
active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and  
the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this  
period has expired and SWDT has not been set, the WDT is automatically reset, otherwise the watchdog timer is reloaded with  
the content of the WDTREL register and the WDT is automatically reset. Since the WDT requires exact timing, firmware needs  
to be designed with special care in order to avoid unwanted WDT resets.  
TERIDIAN strongly discourages the use of the software WDT.  
V1.0  
© 2005-2008 TERIDIAN Semiconductor Corporation  
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